From: Dmitry Osipenko Date: Tue, 3 Oct 2017 23:02:39 +0000 (+0300) Subject: clk: tegra: Correct parent of the APBDMA clock X-Git-Tag: v4.15-rc1~48^2~16^2~5 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=3ff46fd0b22abbb8d921d7e5657912bfbd41b6f0;p=thirdparty%2Fkernel%2Flinux.git clk: tegra: Correct parent of the APBDMA clock APBDMA represents a clock gate to the APB DMA controller, the actual clock source for the controller is PCLK. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c index f5232d6d203dc..c02711927d791 100644 --- a/drivers/clk/tegra/clk-tegra-periph.c +++ b/drivers/clk/tegra/clk-tegra-periph.c @@ -808,7 +808,7 @@ static struct tegra_periph_init_data gate_clks[] = { GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0), GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0), GATE("ahbdma", "hclk", 33, 0, tegra_clk_ahbdma, 0), - GATE("apbdma", "clk_m", 34, 0, tegra_clk_apbdma, 0), + GATE("apbdma", "pclk", 34, 0, tegra_clk_apbdma, 0), GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0), GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0), GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0),