From: Leon Alrae <leon.alrae@imgtec.com>
Date: Fri, 25 Mar 2016 13:49:35 +0000 (+0000)
Subject: target-mips: check CP0 enabled for CACHE instruction also in R6
X-Git-Tag: v2.6.0-rc0~2^2~4
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=40d48212f934d4deab40ffe84a0f9c4c553d4742;p=thirdparty%2Fqemu.git

target-mips: check CP0 enabled for CACHE instruction also in R6

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---

diff --git a/target-mips/translate.c b/target-mips/translate.c
index a5b8805f777..65f2caff3ef 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -17194,6 +17194,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
         /* Treat as NOP. */
         break;
     case R6_OPC_CACHE:
+        check_cp0_enabled(ctx);
         /* Treat as NOP. */
         break;
     case R6_OPC_SC: