From: Greg Kroah-Hartman Date: Thu, 26 Jan 2023 07:58:07 +0000 (+0100) Subject: 5.10-stable patches X-Git-Tag: v5.10.166~78 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=42957066b586173e946bfe516fbe39a4e6c0b8d2;p=thirdparty%2Fkernel%2Fstable-queue.git 5.10-stable patches added patches: x86-acpi-cstate-optimize-c3-entry-on-amd-cpus.patch --- diff --git a/queue-5.10/series b/queue-5.10/series index b6e41f1c392..0f1996e9581 100644 --- a/queue-5.10/series +++ b/queue-5.10/series @@ -74,3 +74,4 @@ platform-x86-asus-nb-wmi-add-alternate-mapping-for-k.patch lockref-stop-doing-cpu_relax-in-the-cmpxchg-loop.patch revert-selftests-bpf-check-null-propagation-only-nei.patch netfilter-conntrack-do-not-renew-entry-stuck-in-tcp-.patch +x86-acpi-cstate-optimize-c3-entry-on-amd-cpus.patch diff --git a/queue-5.10/x86-acpi-cstate-optimize-c3-entry-on-amd-cpus.patch b/queue-5.10/x86-acpi-cstate-optimize-c3-entry-on-amd-cpus.patch new file mode 100644 index 00000000000..2ca266ea436 --- /dev/null +++ b/queue-5.10/x86-acpi-cstate-optimize-c3-entry-on-amd-cpus.patch @@ -0,0 +1,47 @@ +From a8fb40966f19ff81520d9ccf8f7e2b95201368b8 Mon Sep 17 00:00:00 2001 +From: Deepak Sharma +Date: Thu, 23 Sep 2021 23:12:05 -0700 +Subject: x86: ACPI: cstate: Optimize C3 entry on AMD CPUs + +From: Deepak Sharma + +commit a8fb40966f19ff81520d9ccf8f7e2b95201368b8 upstream. + +All Zen or newer CPU which support C3 shares cache. Its not necessary to +flush the caches in software before entering C3. This will cause drop in +performance for the cores which share some caches. ARB_DIS is not used +with current AMD C state implementation. So set related flags correctly. + +Signed-off-by: Deepak Sharma +Acked-by: Thomas Gleixner +Signed-off-by: Rafael J. Wysocki +Signed-off-by: Guilherme G. Piccoli +Signed-off-by: Greg Kroah-Hartman +--- + arch/x86/kernel/acpi/cstate.c | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +--- a/arch/x86/kernel/acpi/cstate.c ++++ b/arch/x86/kernel/acpi/cstate.c +@@ -79,6 +79,21 @@ void acpi_processor_power_init_bm_check( + */ + flags->bm_control = 0; + } ++ if (c->x86_vendor == X86_VENDOR_AMD && c->x86 >= 0x17) { ++ /* ++ * For all AMD Zen or newer CPUs that support C3, caches ++ * should not be flushed by software while entering C3 ++ * type state. Set bm->check to 1 so that kernel doesn't ++ * need to execute cache flush operation. ++ */ ++ flags->bm_check = 1; ++ /* ++ * In current AMD C state implementation ARB_DIS is no longer ++ * used. So set bm_control to zero to indicate ARB_DIS is not ++ * required while entering C3 type state. ++ */ ++ flags->bm_control = 0; ++ } + } + EXPORT_SYMBOL(acpi_processor_power_init_bm_check); +