From: Ville Syrjälä Date: Tue, 17 Jun 2025 17:07:51 +0000 (+0300) Subject: drm/i915/dmc: Limit pipe DMC clock gating w/a to just ADL/DG2/MTL X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=42a7bf8aa730606ae89b60c1058c50866f240e5d;p=thirdparty%2Fkernel%2Flinux.git drm/i915/dmc: Limit pipe DMC clock gating w/a to just ADL/DG2/MTL Supposedly nothing post-MTL (even BMG) needs the pipe DMC clock gating w/a (Wa_16015201720), so don't apply it. TODO: check if the ADL/DG2 "clock gating needed during DMC loading" part is actually needed, not seeing anything in the docs about it... Reviewed-by: Uma Shankar Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20250617170759.19552-2-ville.syrjala@linux.intel.com --- diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index 1295d8245a2ee..1d748b9dca443 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -488,7 +488,7 @@ static void mtl_pipedmc_clock_gating_wa(struct intel_display *display) static void pipedmc_clock_gating_wa(struct intel_display *display, bool enable) { - if (DISPLAY_VER(display) >= 14 && enable) + if (display->platform.meteorlake && enable) mtl_pipedmc_clock_gating_wa(display); else if (DISPLAY_VER(display) == 13) adlp_pipedmc_clock_gating_wa(display, enable);