From: Greg Kroah-Hartman Date: Thu, 18 Aug 2016 11:56:30 +0000 (+0200) Subject: 4.4-stable patches X-Git-Tag: v3.14.77~17 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=42c7c1e7564e7ed6a93f59da8475e3816ec5206b;p=thirdparty%2Fkernel%2Fstable-queue.git 4.4-stable patches added patches: drm-edid-add-6-bpc-quirk-for-display-aeo-model-0.patch drm-nouveau-check-for-supported-chipset-before-booting-fbdev-off-the-hw.patch drm-nouveau-fbcon-fix-font-width-not-divisible-by-8.patch drm-nouveau-gr-nv3x-fix-instobj-write-offsets-in-gr-setup.patch drm-restore-double-clflush-on-the-last-partial-cacheline.patch --- diff --git a/queue-4.4/drm-edid-add-6-bpc-quirk-for-display-aeo-model-0.patch b/queue-4.4/drm-edid-add-6-bpc-quirk-for-display-aeo-model-0.patch new file mode 100644 index 00000000000..ddb00954473 --- /dev/null +++ b/queue-4.4/drm-edid-add-6-bpc-quirk-for-display-aeo-model-0.patch @@ -0,0 +1,83 @@ +From e10aec652f31ec61d6a0b4d00d8ef8d2b66fa0fd Mon Sep 17 00:00:00 2001 +From: Mario Kleiner +Date: Wed, 6 Jul 2016 12:05:44 +0200 +Subject: drm/edid: Add 6 bpc quirk for display AEO model 0. +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Mario Kleiner + +commit e10aec652f31ec61d6a0b4d00d8ef8d2b66fa0fd upstream. + +Bugzilla https://bugzilla.kernel.org/show_bug.cgi?id=105331 +reports that the "AEO model 0" display is driven with 8 bpc +without dithering by default, which looks bad because that +panel is apparently a 6 bpc DP panel with faulty EDID. + +A fix for this was made by commit 013dd9e03872 +("drm/i915/dp: fall back to 18 bpp when sink capability is unknown"). + +That commit triggers new regressions in precision for DP->DVI and +DP->VGA displays. A patch is out to revert that commit, but it will +revert video output for the AEO model 0 panel to 8 bpc without +dithering. + +The EDID 1.3 of that panel, as decoded from the xrandr output +attached to that bugzilla bug report, is somewhat faulty, and beyond +other problems also sets the "DFP 1.x compliant TMDS" bit, which +according to DFP spec means to drive the panel with 8 bpc and +no dithering in absence of other colorimetry information. + +Try to make the original bug reporter happy despite the +faulty EDID by adding a quirk to mark that panel as 6 bpc, +so 6 bpc output with dithering creates a nice picture. + +Tested by injecting the edid from the fdo bug into a DP connector +via drm_kms_helper.edid_firmware and verifying the 6 bpc + dithering +is selected. + +This patch should be backported to stable. + +Signed-off-by: Mario Kleiner +Cc: Jani Nikula +Cc: Ville Syrjälä +Cc: Daniel Vetter +Signed-off-by: Dave Airlie +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/drm_edid.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/drivers/gpu/drm/drm_edid.c ++++ b/drivers/gpu/drm/drm_edid.c +@@ -73,6 +73,8 @@ + #define EDID_QUIRK_FORCE_8BPC (1 << 8) + /* Force 12bpc */ + #define EDID_QUIRK_FORCE_12BPC (1 << 9) ++/* Force 6bpc */ ++#define EDID_QUIRK_FORCE_6BPC (1 << 10) + + struct detailed_mode_closure { + struct drm_connector *connector; +@@ -99,6 +101,9 @@ static struct edid_quirk { + /* Unknown Acer */ + { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, + ++ /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ ++ { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, ++ + /* Belinea 10 15 55 */ + { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, + { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, +@@ -3820,6 +3825,9 @@ int drm_add_edid_modes(struct drm_connec + + drm_add_display_info(edid, &connector->display_info, connector); + ++ if (quirks & EDID_QUIRK_FORCE_6BPC) ++ connector->display_info.bpc = 6; ++ + if (quirks & EDID_QUIRK_FORCE_8BPC) + connector->display_info.bpc = 8; + diff --git a/queue-4.4/drm-nouveau-check-for-supported-chipset-before-booting-fbdev-off-the-hw.patch b/queue-4.4/drm-nouveau-check-for-supported-chipset-before-booting-fbdev-off-the-hw.patch new file mode 100644 index 00000000000..5cba2a062cd --- /dev/null +++ b/queue-4.4/drm-nouveau-check-for-supported-chipset-before-booting-fbdev-off-the-hw.patch @@ -0,0 +1,36 @@ +From 0e67bed2c765ff0fdaec62c963881f5416fe3692 Mon Sep 17 00:00:00 2001 +From: Ben Skeggs +Date: Tue, 12 Jul 2016 11:57:07 +1000 +Subject: drm/nouveau: check for supported chipset before booting fbdev off the hw + +From: Ben Skeggs + +commit 0e67bed2c765ff0fdaec62c963881f5416fe3692 upstream. + +Signed-off-by: Ben Skeggs +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/nouveau/nouveau_drm.c | 11 ++++++++++- + 1 file changed, 10 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/nouveau/nouveau_drm.c ++++ b/drivers/gpu/drm/nouveau/nouveau_drm.c +@@ -308,7 +308,16 @@ static int nouveau_drm_probe(struct pci_ + bool boot = false; + int ret; + +- /* remove conflicting drivers (vesafb, efifb etc) */ ++ /* We need to check that the chipset is supported before booting ++ * fbdev off the hardware, as there's no way to put it back. ++ */ ++ ret = nvkm_device_pci_new(pdev, NULL, "error", true, false, 0, &device); ++ if (ret) ++ return ret; ++ ++ nvkm_device_del(&device); ++ ++ /* Remove conflicting drivers (vesafb, efifb etc). */ + aper = alloc_apertures(3); + if (!aper) + return -ENOMEM; diff --git a/queue-4.4/drm-nouveau-fbcon-fix-font-width-not-divisible-by-8.patch b/queue-4.4/drm-nouveau-fbcon-fix-font-width-not-divisible-by-8.patch new file mode 100644 index 00000000000..b265693873f --- /dev/null +++ b/queue-4.4/drm-nouveau-fbcon-fix-font-width-not-divisible-by-8.patch @@ -0,0 +1,76 @@ +From 28668f43b8e421634e1623f72a879812288dd06b Mon Sep 17 00:00:00 2001 +From: Mikulas Patocka +Date: Thu, 28 Jul 2016 18:56:13 -0400 +Subject: drm/nouveau/fbcon: fix font width not divisible by 8 + +From: Mikulas Patocka + +commit 28668f43b8e421634e1623f72a879812288dd06b upstream. + +The patch f045f459d925 ("drm/nouveau/fbcon: fix out-of-bounds memory accesses") +tries to fix some out of memory accesses. Unfortunatelly, the patch breaks the +display when using fonts with width that is not divisiable by 8. + +The monochrome bitmap for each character is stored in memory by lines from top +to bottom. Each line is padded to a full byte. + +For example, for 22x11 font, each line is padded to 16 bits, so each +character is consuming 44 bytes total, that is 11 32-bit words. The patch +f045f459d925 changed the logic to "dsize = ALIGN(image->width * +image->height, 32) >> 5", that is just 8 words - this is incorrect and it +causes display corruption. + +This patch adds the necesary padding of lines to 8 bytes. + +This patch should be backported to stable kernels where f045f459d925 was +backported. + +Signed-off-by: Mikulas Patocka +Fixes: f045f459d925 ("drm/nouveau/fbcon: fix out-of-bounds memory accesses") +Signed-off-by: Ben Skeggs +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/nouveau/nv04_fbcon.c | 4 ++-- + drivers/gpu/drm/nouveau/nv50_fbcon.c | 2 +- + drivers/gpu/drm/nouveau/nvc0_fbcon.c | 2 +- + 3 files changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/gpu/drm/nouveau/nv04_fbcon.c ++++ b/drivers/gpu/drm/nouveau/nv04_fbcon.c +@@ -107,11 +107,11 @@ nv04_fbcon_imageblit(struct fb_info *inf + ((image->dx + image->width) & 0xffff)); + OUT_RING(chan, bg); + OUT_RING(chan, fg); +- OUT_RING(chan, (image->height << 16) | image->width); ++ OUT_RING(chan, (image->height << 16) | ALIGN(image->width, 8)); + OUT_RING(chan, (image->height << 16) | image->width); + OUT_RING(chan, (image->dy << 16) | (image->dx & 0xffff)); + +- dsize = ALIGN(image->width * image->height, 32) >> 5; ++ dsize = ALIGN(ALIGN(image->width, 8) * image->height, 32) >> 5; + while (dsize) { + int iter_len = dsize > 128 ? 128 : dsize; + +--- a/drivers/gpu/drm/nouveau/nv50_fbcon.c ++++ b/drivers/gpu/drm/nouveau/nv50_fbcon.c +@@ -125,7 +125,7 @@ nv50_fbcon_imageblit(struct fb_info *inf + OUT_RING(chan, 0); + OUT_RING(chan, image->dy); + +- dwords = ALIGN(image->width * image->height, 32) >> 5; ++ dwords = ALIGN(ALIGN(image->width, 8) * image->height, 32) >> 5; + while (dwords) { + int push = dwords > 2047 ? 2047 : dwords; + +--- a/drivers/gpu/drm/nouveau/nvc0_fbcon.c ++++ b/drivers/gpu/drm/nouveau/nvc0_fbcon.c +@@ -125,7 +125,7 @@ nvc0_fbcon_imageblit(struct fb_info *inf + OUT_RING (chan, 0); + OUT_RING (chan, image->dy); + +- dwords = ALIGN(image->width * image->height, 32) >> 5; ++ dwords = ALIGN(ALIGN(image->width, 8) * image->height, 32) >> 5; + while (dwords) { + int push = dwords > 2047 ? 2047 : dwords; + diff --git a/queue-4.4/drm-nouveau-gr-nv3x-fix-instobj-write-offsets-in-gr-setup.patch b/queue-4.4/drm-nouveau-gr-nv3x-fix-instobj-write-offsets-in-gr-setup.patch new file mode 100644 index 00000000000..3353ae3179e --- /dev/null +++ b/queue-4.4/drm-nouveau-gr-nv3x-fix-instobj-write-offsets-in-gr-setup.patch @@ -0,0 +1,49 @@ +From d0e62ef6ed257715a88d0e5d7cd850a1695429e2 Mon Sep 17 00:00:00 2001 +From: Ilia Mirkin +Date: Wed, 27 Jul 2016 19:16:39 -0400 +Subject: drm/nouveau/gr/nv3x: fix instobj write offsets in gr setup + +From: Ilia Mirkin + +commit d0e62ef6ed257715a88d0e5d7cd850a1695429e2 upstream. + +This should fix some unaligned access warnings. This is also likely to +fix non-descript issues on nv30/nv34 as a result of incorrect channel +setup. + +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96836 +Signed-off-by: Ilia Mirkin +Signed-off-by: Ben Skeggs +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c | 4 ++-- + drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c | 4 ++-- + 2 files changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c ++++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c +@@ -76,8 +76,8 @@ nv30_gr_chan_new(struct nvkm_gr *base, s + nvkm_wo32(chan->inst, i, 0x00040004); + for (i = 0x1f18; i <= 0x3088 ; i += 16) { + nvkm_wo32(chan->inst, i + 0, 0x10700ff9); +- nvkm_wo32(chan->inst, i + 1, 0x0436086c); +- nvkm_wo32(chan->inst, i + 2, 0x000c001b); ++ nvkm_wo32(chan->inst, i + 4, 0x0436086c); ++ nvkm_wo32(chan->inst, i + 8, 0x000c001b); + } + for (i = 0x30b8; i < 0x30c8; i += 4) + nvkm_wo32(chan->inst, i, 0x0000ffff); +--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c ++++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c +@@ -75,8 +75,8 @@ nv34_gr_chan_new(struct nvkm_gr *base, s + nvkm_wo32(chan->inst, i, 0x00040004); + for (i = 0x15ac; i <= 0x271c ; i += 16) { + nvkm_wo32(chan->inst, i + 0, 0x10700ff9); +- nvkm_wo32(chan->inst, i + 1, 0x0436086c); +- nvkm_wo32(chan->inst, i + 2, 0x000c001b); ++ nvkm_wo32(chan->inst, i + 4, 0x0436086c); ++ nvkm_wo32(chan->inst, i + 8, 0x000c001b); + } + for (i = 0x274c; i < 0x275c; i += 4) + nvkm_wo32(chan->inst, i, 0x0000ffff); diff --git a/queue-4.4/drm-restore-double-clflush-on-the-last-partial-cacheline.patch b/queue-4.4/drm-restore-double-clflush-on-the-last-partial-cacheline.patch new file mode 100644 index 00000000000..fecb4433135 --- /dev/null +++ b/queue-4.4/drm-restore-double-clflush-on-the-last-partial-cacheline.patch @@ -0,0 +1,54 @@ +From 396f5d62d1a5fd99421855a08ffdef8edb43c76e Mon Sep 17 00:00:00 2001 +From: Chris Wilson +Date: Thu, 7 Jul 2016 09:41:12 +0100 +Subject: drm: Restore double clflush on the last partial cacheline + +From: Chris Wilson + +commit 396f5d62d1a5fd99421855a08ffdef8edb43c76e upstream. + +This effectively reverts + +commit afcd950cafea6e27b739fe7772cbbeed37d05b8b +Author: Chris Wilson +Date: Wed Jun 10 15:58:01 2015 +0100 + + drm: Avoid the double clflush on the last cache line in drm_clflush_virt_range() + +as we have observed issues with serialisation of the clflush operations +on Baytrail+ Atoms with partial updates. Applying the double flush on the +last cacheline forces that clflush to be ordered with respect to the +previous clflush, and the mfence then protects against prefetches crossing +the clflush boundary. + +The same issue can be demonstrated in userspace with igt/gem_exec_flush. + +Fixes: afcd950cafea6 (drm: Avoid the double clflush on the last cache...) +Testcase: igt/gem_concurrent_blit +Testcase: igt/gem_partial_pread_pwrite +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92845 +Signed-off-by: Chris Wilson +Cc: dri-devel@lists.freedesktop.org +Cc: Akash Goel +Cc: Imre Deak +Cc: Daniel Vetter +Cc: Jason Ekstrand +Reviewed-by: Mika Kuoppala +Signed-off-by: Daniel Vetter +Link: http://patchwork.freedesktop.org/patch/msgid/1467880930-23082-6-git-send-email-chris@chris-wilson.co.uk +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/drm_cache.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/gpu/drm/drm_cache.c ++++ b/drivers/gpu/drm/drm_cache.c +@@ -136,6 +136,7 @@ drm_clflush_virt_range(void *addr, unsig + mb(); + for (; addr < end; addr += size) + clflushopt(addr); ++ clflushopt(end - 1); /* force serialisation */ + mb(); + return; + } diff --git a/queue-4.4/series b/queue-4.4/series index 2bb8d430ad4..8be3dacbf20 100644 --- a/queue-4.4/series +++ b/queue-4.4/series @@ -82,3 +82,8 @@ drm-radeon-add-a-delay-after-atpx-dgpu-power-off.patch drm-radeon-poll-for-both-connect-disconnect-on-analog-connectors.patch drm-radeon-fix-firmware-info-version-checks.patch drm-radeon-support-backlight-control-for-uniphy3.patch +drm-nouveau-check-for-supported-chipset-before-booting-fbdev-off-the-hw.patch +drm-nouveau-gr-nv3x-fix-instobj-write-offsets-in-gr-setup.patch +drm-nouveau-fbcon-fix-font-width-not-divisible-by-8.patch +drm-restore-double-clflush-on-the-last-partial-cacheline.patch +drm-edid-add-6-bpc-quirk-for-display-aeo-model-0.patch