From: Greg Kroah-Hartman Date: Wed, 2 Nov 2011 16:31:41 +0000 (-0700) Subject: 3.0 patches X-Git-Tag: v3.0.9~42 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=433ee9d0c4fda287d19ce313f4f7e3fb7c5e3f71;p=thirdparty%2Fkernel%2Fstable-queue.git 3.0 patches --- diff --git a/queue-3.0/arm-mach-ux500-unlock-i-d-l2x0-caches-before-init.patch b/queue-3.0/arm-mach-ux500-unlock-i-d-l2x0-caches-before-init.patch new file mode 100644 index 00000000000..2f1e4a8a7f5 --- /dev/null +++ b/queue-3.0/arm-mach-ux500-unlock-i-d-l2x0-caches-before-init.patch @@ -0,0 +1,72 @@ +From 1bf6d2c1bb23533af6930581cc39b74685bc29de Mon Sep 17 00:00:00 2001 +From: Linus Walleij +Date: Fri, 12 Aug 2011 13:54:42 +0200 +Subject: ARM: mach-ux500: unlock I&D l2x0 caches before init + +From: Linus Walleij + +commit 1bf6d2c1bb23533af6930581cc39b74685bc29de upstream. + +Apparently U8500 U-Boot versions may leave the l2x0 locked down +before executing the kernel. Make sure we unlock it before we +initialize the l2x0. This fixes a performance problem reported +by Jan Rinze. + +The l2x0 core has been modified to unlock the l2x0 by default, +but it will not touch the locking registers if the l2x0 was +already enabled, as on the ux500, so we need this quirk to +make sure it is properly turned off. + +Cc: Srinidhi Kasagar +Cc: Rabin Vincent +Cc: Adrian Bunk +Reported-by: Jan Rinze +Tested-by: Robert Marklund +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/mach-ux500/cpu.c | 25 ++++++++++++++++++++++++- + 1 file changed, 24 insertions(+), 1 deletion(-) + +--- a/arch/arm/mach-ux500/cpu.c ++++ b/arch/arm/mach-ux500/cpu.c +@@ -99,7 +99,27 @@ static void ux500_l2x0_inv_all(void) + ux500_cache_sync(); + } + +-static int ux500_l2x0_init(void) ++static int __init ux500_l2x0_unlock(void) ++{ ++ int i; ++ ++ /* ++ * Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions ++ * apparently locks both caches before jumping to the kernel. The ++ * l2x0 core will not touch the unlock registers if the l2x0 is ++ * already enabled, so we do it right here instead. The PL310 has ++ * 8 sets of registers, one per possible CPU. ++ */ ++ for (i = 0; i < 8; i++) { ++ writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE + ++ i * L2X0_LOCKDOWN_STRIDE); ++ writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE + ++ i * L2X0_LOCKDOWN_STRIDE); ++ } ++ return 0; ++} ++ ++static int __init ux500_l2x0_init(void) + { + if (cpu_is_u5500()) + l2x0_base = __io_address(U5500_L2CC_BASE); +@@ -108,6 +128,9 @@ static int ux500_l2x0_init(void) + else + ux500_unknown_soc(); + ++ /* Unlock before init */ ++ ux500_l2x0_unlock(); ++ + /* 64KB way size, 8 way associativity, force WA */ + l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff); + diff --git a/queue-3.0/plat-mxc-iomux-v3.h-implicitly-enable-pull-up-down-when-that-s-desired.patch b/queue-3.0/plat-mxc-iomux-v3.h-implicitly-enable-pull-up-down-when-that-s-desired.patch new file mode 100644 index 00000000000..17e66fe452c --- /dev/null +++ b/queue-3.0/plat-mxc-iomux-v3.h-implicitly-enable-pull-up-down-when-that-s-desired.patch @@ -0,0 +1,52 @@ +From 6571534b600b8ca1936ff5630b9e0947f21faf16 Mon Sep 17 00:00:00 2001 +From: Paul Fertser +Date: Mon, 10 Oct 2011 11:19:23 +0400 +Subject: plat-mxc: iomux-v3.h: implicitly enable pull-up/down when that's desired + +From: Paul Fertser + +commit 6571534b600b8ca1936ff5630b9e0947f21faf16 upstream. + +To configure pads during the initialisation a set of special constants +is used, e.g. +#define MX25_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x3c4, 0x1cc, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP) + +The problem is that no pull-up/down is getting activated unless both +PAD_CTL_PUE (pull-up enable) and PAD_CTL_PKE (pull/keeper module +enable) set. This is clearly stated in the i.MX25 datasheet and is +confirmed by the measurements on hardware. This leads to some rather +hard to understand bugs such as misdetecting an absent ethernet PHY (a +real bug i had), unstable data transfer etc. This might affect mx25, +mx35, mx50, mx51 and mx53 SoCs. + +It's reasonable to expect that if the pullup value is specified, the +intention was to have it actually active, so we implicitly add the +needed bits. + +Signed-off-by: Paul Fertser +Signed-off-by: Sascha Hauer +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/plat-mxc/include/mach/iomux-v3.h | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h ++++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h +@@ -89,11 +89,11 @@ typedef u64 iomux_v3_cfg_t; + #define PAD_CTL_HYS (1 << 8) + + #define PAD_CTL_PKE (1 << 7) +-#define PAD_CTL_PUE (1 << 6) +-#define PAD_CTL_PUS_100K_DOWN (0 << 4) +-#define PAD_CTL_PUS_47K_UP (1 << 4) +-#define PAD_CTL_PUS_100K_UP (2 << 4) +-#define PAD_CTL_PUS_22K_UP (3 << 4) ++#define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE) ++#define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE) ++#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE) ++#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE) ++#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE) + + #define PAD_CTL_ODE (1 << 3) + diff --git a/queue-3.0/series b/queue-3.0/series index da04bef9a4b..1a3e942bcee 100644 --- a/queue-3.0/series +++ b/queue-3.0/series @@ -120,3 +120,5 @@ dibcom-protect-the-i2c-bufer-access.patch dib0700-protect-the-dib0700-buffer-access.patch tuner_xc2028-allow-selection-of-the-frequency-adjustment-code-for-xc3028.patch proc-self-numa_maps-restore-huge-tag-for-hugetlb-vmas.patch +plat-mxc-iomux-v3.h-implicitly-enable-pull-up-down-when-that-s-desired.patch +arm-mach-ux500-unlock-i-d-l2x0-caches-before-init.patch