From: Jan Beulich <jbeulich@suse.com>
Date: Fri, 31 Jan 2025 09:07:54 +0000 (+0100)
Subject: x86/APX: correct libbfd's EVEX Rn -> Bn transformations
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=43a7719af5aea466d8c7ac70742fb8e06d4bcf29;p=thirdparty%2Fbinutils-gdb.git

x86/APX: correct libbfd's EVEX Rn -> Bn transformations

In the recent GOTPCREL addition I screwed up, in clearing the Rn bits
afterwards rather than setting them. While that ought to be benign (for
the bits being ignored in situations like this), we still want to leave
"canonical" encodings.

The pre-existing GOTTPOFF conversion wasn't doing quite correctly
either: We cannot assume the incoming Bn bits to be in a particular
state, as for the addressing form in question they're ignored as well.

To address both, introduce a helper function. This is then also an
overall reduction of (source) code size (and use of "magic" numbers).
---

diff --git a/bfd/elf64-x86-64.c b/bfd/elf64-x86-64.c
index d1d02bd7b32..61334c3ab04 100644
--- a/bfd/elf64-x86-64.c
+++ b/bfd/elf64-x86-64.c
@@ -1738,6 +1738,16 @@ elf_x86_64_need_pic (struct bfd_link_info *info,
   return false;
 }
 
+/* Move the R bits to the B bits in EVEX payload byte 1.  */
+static unsigned int evex_move_r_to_b (unsigned int byte1)
+{
+  byte1 = (byte1 & ~(1 << 5)) | ((byte1 & (1 << 7)) >> 2); /* R3 -> B3 */
+  byte1 = (byte1 & ~(1 << 3)) | ((~byte1 & (1 << 4)) >> 1); /* R4 -> B4 */
+
+  /* Set both R bits, as they're inverted.  */
+  return byte1 | (1 << 4) | (1 << 7);
+}
+
 /* With the local symbol, foo, we convert
    mov foo@GOTPCREL(%rip), %reg
    movrs foo@GOTPCREL(%rip), %reg
@@ -2109,9 +2119,7 @@ elf_x86_64_convert_load_reloc (bfd *abfd,
       bfd_put_8 (abfd, opcode, contents + roff - 2);
       bfd_put_8 (abfd, modrm, contents + roff - 1);
 
-      /* Move the R bits to the B bits in the first EXEX payload byte.  */
-      evex[0] = (evex[0] & ~0xa0) | ((evex[0] & 0x80) >> 2); /* R3 -> B3 */
-      evex[0] = (evex[0] & ~0x18) | ((~evex[0] & 0x10) >> 1); /* R4 -> B4 */
+      evex[0] = evex_move_r_to_b (evex[0]);
       bfd_put_8 (abfd, evex[0], contents + roff - 5);
 
       /* No addend for R_X86_64_32/R_X86_64_32S relocations.  */
@@ -4333,7 +4341,6 @@ elf_x86_64_relocate_section (bfd *output_bfd,
 		     mov $foo@tpoff, %reg
 		     where reg is one of r16 to r31.  */
 		  unsigned int type, reg, byte1;
-		  unsigned int updated_byte1;
 
 		  if (roff < 6)
 		    goto corrupt_input;
@@ -4371,25 +4378,10 @@ elf_x86_64_relocate_section (bfd *output_bfd,
 		      continue;
 		    }
 
-		  /* Move the R bits to the B bits in EVEX payload
-		     byte 1.  */
-		  updated_byte1 = byte1;
-
-		  /* Set the R bits since they is inverted.  */
-		  updated_byte1 |= 1 << 7 | 1 << 4;
-
-		  /* Update the B bits from the R bits.  */
-		  if ((byte1 & (1 << 7)) == 0)
-		    updated_byte1 &= ~(1 << 5);
-		  if ((byte1 & (1 << 4)) == 0)
-		    updated_byte1 |= 1 << 3;
-
-		  bfd_put_8 (output_bfd, updated_byte1,
-			     contents + roff - 5);
-		  bfd_put_8 (output_bfd, 0x81,
-			     contents + roff - 2);
-		  bfd_put_8 (output_bfd, 0xc0 | reg,
-			     contents + roff - 1);
+		  byte1 = evex_move_r_to_b (byte1);
+		  bfd_put_8 (output_bfd, byte1, contents + roff - 5);
+		  bfd_put_8 (output_bfd, 0x81, contents + roff - 2);
+		  bfd_put_8 (output_bfd, 0xc0 | reg, contents + roff - 1);
 		  bfd_put_32 (output_bfd,
 			      elf_x86_64_tpoff (info, relocation),
 			      contents + roff);
diff --git a/ld/testsuite/ld-x86-64/apx-load1a.d b/ld/testsuite/ld-x86-64/apx-load1a.d
index ce4d167cb93..83d4cd218bb 100644
--- a/ld/testsuite/ld-x86-64/apx-load1a.d
+++ b/ld/testsuite/ld-x86-64/apx-load1a.d
@@ -51,24 +51,24 @@ Disassembly of section .text:
  +[a-f0-9]+:	d5 18 81 ee 21 20 60 00 	sub    \$0x602021,%r22
  +[a-f0-9]+:	d5 18 81 f7 21 20 60 00 	xor    \$0x602021,%r23
  +[a-f0-9]+:	d5 19 f7 c0 21 20 60 00 	test   \$0x602021,%r24
- +[a-f0-9]+:	62 6c 7c 08 81 d0 20 20 60 00 	adc    \$0x602020,%r16d
- +[a-f0-9]+:	62 6c 7c 0c 81 c1 20 20 60 00 	\{nf\} add \$0x602020,%r17d
- +[a-f0-9]+:	62 6c 7c 0c 81 e2 20 20 60 00 	\{nf\} and \$0x602020,%r18d
- +[a-f0-9]+:	62 6c 04 0a 81 fb 20 20 60 00 	ccmpt \{dfv=\} \$0x602020,%r19d
- +[a-f0-9]+:	62 6c 7c 0c 81 cc 20 20 60 00 	\{nf\} or \$0x602020,%r20d
- +[a-f0-9]+:	62 6c 7c 08 81 dd 20 20 60 00 	sbb    \$0x602020,%r21d
- +[a-f0-9]+:	62 6c 7c 0c 81 ee 20 20 60 00 	\{nf\} sub \$0x602020,%r22d
- +[a-f0-9]+:	62 6c 7c 0c 81 f7 20 20 60 00 	\{nf\} xor \$0x602020,%r23d
- +[a-f0-9]+:	62 4c 04 0a f7 c0 20 20 60 00 	ctestt \{dfv=\} \$0x602020,%r24d
- +[a-f0-9]+:	62 6c fc 08 81 d0 20 20 60 00 	adc    \$0x602020,%r16
- +[a-f0-9]+:	62 6c fc 0c 81 c1 20 20 60 00 	\{nf\} add \$0x602020,%r17
- +[a-f0-9]+:	62 6c fc 0c 81 e2 20 20 60 00 	\{nf\} and \$0x602020,%r18
- +[a-f0-9]+:	62 6c 84 0a 81 fb 20 20 60 00 	ccmpt \{dfv=\} \$0x602020,%r19
- +[a-f0-9]+:	62 6c fc 0c 81 cc 20 20 60 00 	\{nf\} or \$0x602020,%r20
- +[a-f0-9]+:	62 6c fc 08 81 dd 20 20 60 00 	sbb    \$0x602020,%r21
- +[a-f0-9]+:	62 6c fc 0c 81 ee 20 20 60 00 	\{nf\} sub \$0x602020,%r22
- +[a-f0-9]+:	62 6c fc 0c 81 f7 20 20 60 00 	\{nf\} xor \$0x602020,%r23
- +[a-f0-9]+:	62 4c 84 0a f7 c0 20 20 60 00 	ctestt \{dfv=\} \$0x602020,%r24
+ +[a-f0-9]+:	62 fc 7c 08 81 d0 20 20 60 00 	adc    \$0x602020,%r16d
+ +[a-f0-9]+:	62 fc 7c 0c 81 c1 20 20 60 00 	\{nf\} add \$0x602020,%r17d
+ +[a-f0-9]+:	62 fc 7c 0c 81 e2 20 20 60 00 	\{nf\} and \$0x602020,%r18d
+ +[a-f0-9]+:	62 fc 04 0a 81 fb 20 20 60 00 	ccmpt \{dfv=\} \$0x602020,%r19d
+ +[a-f0-9]+:	62 fc 7c 0c 81 cc 20 20 60 00 	\{nf\} or \$0x602020,%r20d
+ +[a-f0-9]+:	62 fc 7c 08 81 dd 20 20 60 00 	sbb    \$0x602020,%r21d
+ +[a-f0-9]+:	62 fc 7c 0c 81 ee 20 20 60 00 	\{nf\} sub \$0x602020,%r22d
+ +[a-f0-9]+:	62 fc 7c 0c 81 f7 20 20 60 00 	\{nf\} xor \$0x602020,%r23d
+ +[a-f0-9]+:	62 dc 04 0a f7 c0 20 20 60 00 	ctestt \{dfv=\} \$0x602020,%r24d
+ +[a-f0-9]+:	62 fc fc 08 81 d0 20 20 60 00 	adc    \$0x602020,%r16
+ +[a-f0-9]+:	62 fc fc 0c 81 c1 20 20 60 00 	\{nf\} add \$0x602020,%r17
+ +[a-f0-9]+:	62 fc fc 0c 81 e2 20 20 60 00 	\{nf\} and \$0x602020,%r18
+ +[a-f0-9]+:	62 fc 84 0a 81 fb 20 20 60 00 	ccmpt \{dfv=\} \$0x602020,%r19
+ +[a-f0-9]+:	62 fc fc 0c 81 cc 20 20 60 00 	\{nf\} or \$0x602020,%r20
+ +[a-f0-9]+:	62 fc fc 08 81 dd 20 20 60 00 	sbb    \$0x602020,%r21
+ +[a-f0-9]+:	62 fc fc 0c 81 ee 20 20 60 00 	\{nf\} sub \$0x602020,%r22
+ +[a-f0-9]+:	62 fc fc 0c 81 f7 20 20 60 00 	\{nf\} xor \$0x602020,%r23
+ +[a-f0-9]+:	62 dc 84 0a f7 c0 20 20 60 00 	ctestt \{dfv=\} \$0x602020,%r24
  +[a-f0-9]+:	62 e4 7c 08 11 05 22 0e 20 00 	adc    %r16d,0x200e22\(%rip\)        # 602000 <.*>
  +[a-f0-9]+:	62 e4 7c 0c 01 0d 18 0e 20 00 	\{nf\} add %r17d,0x200e18\(%rip\)        # 602000 <.*>
  +[a-f0-9]+:	62 e4 7c 0c 21 15 0e 0e 20 00 	\{nf\} and %r18d,0x200e0e\(%rip\)        # 602000 <.*>
@@ -77,7 +77,7 @@ Disassembly of section .text:
  +[a-f0-9]+:	62 e4 7c 08 19 2d f0 0d 20 00 	sbb    %r21d,0x200df0\(%rip\)        # 602000 <.*>
  +[a-f0-9]+:	62 e4 7c 0c 29 35 e6 0d 20 00 	\{nf\} sub %r22d,0x200de6\(%rip\)        # 602000 <.*>
  +[a-f0-9]+:	62 e4 7c 0c 31 3d dc 0d 20 00 	\{nf\} xor %r23d,0x200ddc\(%rip\)        # 602000 <.*>
- +[a-f0-9]+:	62 4c 04 0a f7 c0 20 20 60 00 	ctestt \{dfv=\} \$0x602020,%r24d
+ +[a-f0-9]+:	62 dc 04 0a f7 c0 20 20 60 00 	ctestt \{dfv=\} \$0x602020,%r24d
  +[a-f0-9]+:	62 e4 fc 08 11 05 c8 0d 20 00 	adc    %r16,0x200dc8\(%rip\)        # 602000 <.*>
  +[a-f0-9]+:	62 e4 fc 0c 01 0d be 0d 20 00 	\{nf\} add %r17,0x200dbe\(%rip\)        # 602000 <.*>
  +[a-f0-9]+:	62 e4 fc 0c 21 15 b4 0d 20 00 	\{nf\} and %r18,0x200db4\(%rip\)        # 602000 <.*>
@@ -86,33 +86,33 @@ Disassembly of section .text:
  +[a-f0-9]+:	62 e4 fc 08 19 2d 96 0d 20 00 	sbb    %r21,0x200d96\(%rip\)        # 602000 <.*>
  +[a-f0-9]+:	62 e4 fc 0c 29 35 8c 0d 20 00 	\{nf\} sub %r22,0x200d8c\(%rip\)        # 602000 <.*>
  +[a-f0-9]+:	62 e4 fc 0c 31 3d 82 0d 20 00 	\{nf\} xor %r23,0x200d82\(%rip\)        # 602000 <.*>
- +[a-f0-9]+:	62 4c 84 0a f7 c0 20 20 60 00 	ctestt \{dfv=\} \$0x602020,%r24
- +[a-f0-9]+:	62 6c 7c 18 81 d0 20 20 60 00 	adc    \$0x602020,%r16d,%eax
- +[a-f0-9]+:	62 6c 74 18 81 c1 20 20 60 00 	add    \$0x602020,%r17d,%ecx
- +[a-f0-9]+:	62 6c 6c 18 81 e2 20 20 60 00 	and    \$0x602020,%r18d,%edx
- +[a-f0-9]+:	62 6c 64 18 81 cb 20 20 60 00 	or     \$0x602020,%r19d,%ebx
- +[a-f0-9]+:	62 6c 5c 18 81 dc 20 20 60 00 	sbb    \$0x602020,%r20d,%esp
- +[a-f0-9]+:	62 6c 54 18 81 ed 20 20 60 00 	sub    \$0x602020,%r21d,%ebp
- +[a-f0-9]+:	62 6c 4c 18 81 f6 20 20 60 00 	xor    \$0x602020,%r22d,%esi
- +[a-f0-9]+:	62 6c fc 18 81 d0 20 20 60 00 	adc    \$0x602020,%r16,%rax
- +[a-f0-9]+:	62 6c f4 18 81 c1 20 20 60 00 	add    \$0x602020,%r17,%rcx
- +[a-f0-9]+:	62 6c ec 18 81 e2 20 20 60 00 	and    \$0x602020,%r18,%rdx
- +[a-f0-9]+:	62 6c e4 18 81 cb 20 20 60 00 	or     \$0x602020,%r19,%rbx
- +[a-f0-9]+:	62 6c dc 18 81 dc 20 20 60 00 	sbb    \$0x602020,%r20,%rsp
- +[a-f0-9]+:	62 6c d4 18 81 ed 20 20 60 00 	sub    \$0x602020,%r21,%rbp
- +[a-f0-9]+:	62 6c cc 18 81 f6 20 20 60 00 	xor    \$0x602020,%r22,%rsi
- +[a-f0-9]+:	62 64 7c 10 81 d0 20 20 60 00 	adc    \$0x602020,%eax,%r16d
- +[a-f0-9]+:	62 64 74 10 81 c1 20 20 60 00 	add    \$0x602020,%ecx,%r17d
- +[a-f0-9]+:	62 64 6c 10 81 e2 20 20 60 00 	and    \$0x602020,%edx,%r18d
- +[a-f0-9]+:	62 64 64 10 81 cb 20 20 60 00 	or     \$0x602020,%ebx,%r19d
+ +[a-f0-9]+:	62 dc 84 0a f7 c0 20 20 60 00 	ctestt \{dfv=\} \$0x602020,%r24
+ +[a-f0-9]+:	62 fc 7c 18 81 d0 20 20 60 00 	adc    \$0x602020,%r16d,%eax
+ +[a-f0-9]+:	62 fc 74 18 81 c1 20 20 60 00 	add    \$0x602020,%r17d,%ecx
+ +[a-f0-9]+:	62 fc 6c 18 81 e2 20 20 60 00 	and    \$0x602020,%r18d,%edx
+ +[a-f0-9]+:	62 fc 64 18 81 cb 20 20 60 00 	or     \$0x602020,%r19d,%ebx
+ +[a-f0-9]+:	62 fc 5c 18 81 dc 20 20 60 00 	sbb    \$0x602020,%r20d,%esp
+ +[a-f0-9]+:	62 fc 54 18 81 ed 20 20 60 00 	sub    \$0x602020,%r21d,%ebp
+ +[a-f0-9]+:	62 fc 4c 18 81 f6 20 20 60 00 	xor    \$0x602020,%r22d,%esi
+ +[a-f0-9]+:	62 fc fc 18 81 d0 20 20 60 00 	adc    \$0x602020,%r16,%rax
+ +[a-f0-9]+:	62 fc f4 18 81 c1 20 20 60 00 	add    \$0x602020,%r17,%rcx
+ +[a-f0-9]+:	62 fc ec 18 81 e2 20 20 60 00 	and    \$0x602020,%r18,%rdx
+ +[a-f0-9]+:	62 fc e4 18 81 cb 20 20 60 00 	or     \$0x602020,%r19,%rbx
+ +[a-f0-9]+:	62 fc dc 18 81 dc 20 20 60 00 	sbb    \$0x602020,%r20,%rsp
+ +[a-f0-9]+:	62 fc d4 18 81 ed 20 20 60 00 	sub    \$0x602020,%r21,%rbp
+ +[a-f0-9]+:	62 fc cc 18 81 f6 20 20 60 00 	xor    \$0x602020,%r22,%rsi
+ +[a-f0-9]+:	62 f4 7c 10 81 d0 20 20 60 00 	adc    \$0x602020,%eax,%r16d
+ +[a-f0-9]+:	62 f4 74 10 81 c1 20 20 60 00 	add    \$0x602020,%ecx,%r17d
+ +[a-f0-9]+:	62 f4 6c 10 81 e2 20 20 60 00 	and    \$0x602020,%edx,%r18d
+ +[a-f0-9]+:	62 f4 64 10 81 cb 20 20 60 00 	or     \$0x602020,%ebx,%r19d
  +[a-f0-9]+:	62 f4 5c 10 19 25 ba 0c 20 00 	sbb    %esp,0x200cba\(%rip\),%r20d        # 602000 <.*>
  +[a-f0-9]+:	62 f4 54 10 29 2d b0 0c 20 00 	sub    %ebp,0x200cb0\(%rip\),%r21d        # 602000 <.*>
- +[a-f0-9]+:	62 64 4c 10 81 f6 20 20 60 00 	xor    \$0x602020,%esi,%r22d
- +[a-f0-9]+:	62 64 fc 10 81 d0 20 20 60 00 	adc    \$0x602020,%rax,%r16
- +[a-f0-9]+:	62 64 f4 10 81 c1 20 20 60 00 	add    \$0x602020,%rcx,%r17
- +[a-f0-9]+:	62 64 ec 10 81 e2 20 20 60 00 	and    \$0x602020,%rdx,%r18
- +[a-f0-9]+:	62 64 e4 10 81 cb 20 20 60 00 	or     \$0x602020,%rbx,%r19
+ +[a-f0-9]+:	62 f4 4c 10 81 f6 20 20 60 00 	xor    \$0x602020,%esi,%r22d
+ +[a-f0-9]+:	62 f4 fc 10 81 d0 20 20 60 00 	adc    \$0x602020,%rax,%r16
+ +[a-f0-9]+:	62 f4 f4 10 81 c1 20 20 60 00 	add    \$0x602020,%rcx,%r17
+ +[a-f0-9]+:	62 f4 ec 10 81 e2 20 20 60 00 	and    \$0x602020,%rdx,%r18
+ +[a-f0-9]+:	62 f4 e4 10 81 cb 20 20 60 00 	or     \$0x602020,%rbx,%r19
  +[a-f0-9]+:	62 f4 dc 10 19 25 74 0c 20 00 	sbb    %rsp,0x200c74\(%rip\),%r20        # 602000 <.*>
  +[a-f0-9]+:	62 f4 d4 10 29 2d 6a 0c 20 00 	sub    %rbp,0x200c6a\(%rip\),%r21        # 602000 <.*>
- +[a-f0-9]+:	62 64 cc 10 81 f6 20 20 60 00 	xor    \$0x602020,%rsi,%r22
+ +[a-f0-9]+:	62 f4 cc 10 81 f6 20 20 60 00 	xor    \$0x602020,%rsi,%r22
 #pass