From: Peter Maydell Date: Mon, 20 Mar 2017 12:41:44 +0000 (+0000) Subject: arm: Don't decode MRS(banked) or MSR(banked) for M profile X-Git-Tag: v2.9.0-rc1~8^2~2 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=43ac65742319ef5ac4461daf43316b189cd21e89;p=thirdparty%2Fqemu.git arm: Don't decode MRS(banked) or MSR(banked) for M profile M profile doesn't have the MSR(banked) and MRS(banked) instructions and uses the encodings for different kinds of M-profile MRS/MSR. Guard the relevant bits of the decode logic to make sure we don't accidentally fall into them by accident on M-profile. (The bit being checked for this (bit 5) is part of the SYSm field on M-profile, but since no currently allocated system registers have encodings with bit 5 of SYSm set, this hasn't been a problem in practice.) Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée Message-id: 1487616072-9226-3-git-send-email-peter.maydell@linaro.org --- diff --git a/target/arm/translate.c b/target/arm/translate.c index 216852b6730..a5f5a28ba42 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10500,7 +10500,8 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw gen_exception_return(s, tmp); break; case 6: /* MRS */ - if (extract32(insn, 5, 1)) { + if (extract32(insn, 5, 1) && + !arm_dc_feature(s, ARM_FEATURE_M)) { /* MRS (banked) */ int sysm = extract32(insn, 16, 4) | (extract32(insn, 4, 1) << 4); @@ -10521,7 +10522,8 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw store_reg(s, rd, tmp); break; case 7: /* MRS */ - if (extract32(insn, 5, 1)) { + if (extract32(insn, 5, 1) && + !arm_dc_feature(s, ARM_FEATURE_M)) { /* MRS (banked) */ int sysm = extract32(insn, 16, 4) | (extract32(insn, 4, 1) << 4);