From: Yao Qi <yao.qi@linaro.org>
Date: Mon, 5 Oct 2015 10:15:58 +0000 (+0100)
Subject: Pass noaliases_p to aarch64_decode_insn
X-Git-Tag: users/hjl/linux/release/2.25.51.0.4~1^2~5^2
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=43cdf5aeb8ae6ac2ec3bdbf636cbb2731ccbbb2a;p=thirdparty%2Fbinutils-gdb.git

Pass noaliases_p to aarch64_decode_insn

Nowadays aarch64_decode_insn is a public interface used by both
opcodes and gdb.  However, its behaviour relies on a global variable
no_aliases, which isn't a good practise.  On the other hand, In default,
no_aliases is zero, but in GDB, we do want no alias when decoding
instructions for prologue analysis (patches to be posted), so that we
can handle both instructions "add" and "mov" (an alias of "add") as
"add".  The code in GDB can be simplified.

This patch adds a new argument in aarch64_decode_insn, and pass no_aliases
to it.  In GDB side, always pass 1 to it.

include/opcode:

2015-10-28  Yao Qi  <yao.qi@linaro.org>

	* aarch64.h (aarch64_decode_insn): Update declaration.

opcodes:

2015-10-28  Yao Qi  <yao.qi@linaro.org>

	* aarch64-dis.c	(aarch64_decode_insn): Add one argument
	noaliases_p.  Update comments.  Pass noaliases_p rather than
	no_aliases to aarch64_opcode_decode.
	(print_insn_aarch64_word): Pass no_aliases to
	aarch64_decode_insn.

gdb:

2015-10-28  Yao Qi  <yao.qi@linaro.org>

	* aarch64-tdep.c (aarch64_software_single_step): Pass 1 to
	aarch64_decode_insn.
---

diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index 093619421ec..181991ae4b0 100644
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,8 @@
+2015-10-28  Yao Qi  <yao.qi@linaro.org>
+
+	* aarch64-tdep.c (aarch64_software_single_step): Pass 1 to
+	aarch64_decode_insn.
+
 2015-10-27  Pedro Alves  <palves@redhat.com>
 
 	* common/print-utils.c (host_address_to_string): Rename to ...
diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index 55c5fb86fcc..d01a83f8b3f 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -2499,7 +2499,7 @@ aarch64_software_single_step (struct frame_info *frame)
   int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed).  */
   aarch64_inst inst;
 
-  if (aarch64_decode_insn (insn, &inst) != 0)
+  if (aarch64_decode_insn (insn, &inst, 1) != 0)
     return 0;
 
   /* Look for a Load Exclusive instruction which begins the sequence.  */
@@ -2512,7 +2512,7 @@ aarch64_software_single_step (struct frame_info *frame)
       insn = read_memory_unsigned_integer (loc, insn_size,
 					   byte_order_for_code);
 
-      if (aarch64_decode_insn (insn, &inst) != 0)
+      if (aarch64_decode_insn (insn, &inst, 1) != 0)
 	return 0;
       /* Check if the instruction is a conditional branch.  */
       if (inst.opcode->iclass == condbranch)
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index ea833f73657..b049302318b 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,7 @@
+2015-10-28  Yao Qi  <yao.qi@linaro.org>
+
+	* aarch64.h (aarch64_decode_insn): Update declaration.
+
 2015-10-07  Yao Qi  <yao.qi@linaro.org>
 
 	* aarch64.h (aarch64_sys_ins_reg) <template>: Removed.
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index c423858bb7c..711f7e5cf8e 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -930,7 +930,7 @@ extern int
 aarch64_zero_register_p (const aarch64_opnd_info *);
 
 extern int
-aarch64_decode_insn (aarch64_insn, aarch64_inst *);
+aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean);
 
 /* Given an operand qualifier, return the expected data element size
    of a qualified operand.  */
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index d0f77716a71..89528726a65 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,11 @@
+2015-10-28  Yao Qi  <yao.qi@linaro.org>
+
+	* aarch64-dis.c	(aarch64_decode_insn): Add one argument
+	noaliases_p.  Update comments.  Pass noaliases_p rather than
+	no_aliases to aarch64_opcode_decode.
+	(print_insn_aarch64_word): Pass no_aliases to
+	aarch64_decode_insn.
+
 2015-10-27  Vinay  <Vinay.G@kpit.com>
 
 	PR binutils/19159
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 9b96cff572f..93766c6164a 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -2029,11 +2029,13 @@ user_friendly_fixup (aarch64_inst *inst)
     }
 }
 
-/* Decode INSN and fill in *INST the instruction information.  Return zero
-   on success.  */
+/* Decode INSN and fill in *INST the instruction information.  An alias
+   opcode may be filled in *INSN if NOALIASES_P is FALSE.  Return zero on
+   success.  */
 
 int
-aarch64_decode_insn (aarch64_insn insn, aarch64_inst *inst)
+aarch64_decode_insn (aarch64_insn insn, aarch64_inst *inst,
+		     bfd_boolean noaliases_p)
 {
   const aarch64_opcode *opcode = aarch64_opcode_lookup (insn);
 
@@ -2060,7 +2062,7 @@ aarch64_decode_insn (aarch64_insn insn, aarch64_inst *inst)
     {
       /* But only one opcode can be decoded successfully for, as the
 	 decoding routine will check the constraint carefully.  */
-      if (aarch64_opcode_decode (opcode, insn, inst, no_aliases) == 1)
+      if (aarch64_opcode_decode (opcode, insn, inst, noaliases_p) == 1)
 	return ERR_OK;
       opcode = aarch64_find_next_opcode (opcode);
     }
@@ -2172,7 +2174,7 @@ print_insn_aarch64_word (bfd_vma pc,
        addresses, since the addend is not currently pc-relative.  */
     pc = 0;
 
-  ret = aarch64_decode_insn (word, &inst);
+  ret = aarch64_decode_insn (word, &inst, no_aliases);
 
   if (((word >> 21) & 0x3ff) == 1)
     {