From: renlin <renlin@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Fri, 2 Oct 2015 12:52:36 +0000 (+0000)
Subject: [PATCH][AARCH64]Add csneg3_uxtw_insn pattern
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=446e1fdf52f7399d390b623600947899eae9eef9;p=thirdparty%2Fgcc.git

[PATCH][AARCH64]Add csneg3_uxtw_insn pattern

gcc/

2015-10-02  Renlin Li <renlin.li@arm.com>

	* config/aarch64/aarch64.md (csneg3_uxtw_insn): New pattern.

gcc/testsuite/

2015-10-02  Renlin Li <renlin.li@arm.com>

	* gcc.target/aarch64/csneg-1.c: Update test.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@228387 138bc75d-0d04-0410-961f-82ee72b054a4
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a84b8a9f31f5..57a5a43ffb9a 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -3,6 +3,10 @@
 	* config/sh/sh.md: Add new unnamed split pattern to handle movt-movt
 	sequences.
 
+2015-10-02  Renlin Li  <renlin.li@arm.com>
+
+	* config/aarch64/aarch64.md (csneg3_insn_uxtw): New pattern.
+
 2015-10-02  Renlin Li  <renlin.li@arm.com>
 
 	PR target/66776
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 20681cda431e..74522f861051 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -3144,6 +3144,18 @@
   [(set_attr "type" "csel")]
 )
 
+(define_insn "csneg3_uxtw_insn"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(zero_extend:DI
+	  (if_then_else:SI
+	    (match_operand 1 "aarch64_comparison_operation" "")
+	    (neg:SI (match_operand:SI 2 "register_operand" "r"))
+	    (match_operand:SI 3 "aarch64_reg_or_zero" "rZ"))))]
+  ""
+  "csneg\\t%w0, %w3, %w2, %M1"
+  [(set_attr "type" "csel")]
+)
+
 (define_insn "csneg3<mode>_insn"
   [(set (match_operand:GPI 0 "register_operand" "=r")
         (if_then_else:GPI
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 87bcd8b1256e..c95cda9e0d9b 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2015-10-02  Renlin Li  <renlin.li@arm.com>
+
+	* gcc.target/aarch64/csneg-1.c: Update.
+
 2015-10-02  Renlin Li  <renlin.li@arm.com>
 
 	PR target/66776
diff --git a/gcc/testsuite/gcc.target/aarch64/csneg-1.c b/gcc/testsuite/gcc.target/aarch64/csneg-1.c
index 29d4e4ee70ff..4860d64c9353 100644
--- a/gcc/testsuite/gcc.target/aarch64/csneg-1.c
+++ b/gcc/testsuite/gcc.target/aarch64/csneg-1.c
@@ -56,3 +56,15 @@ int test_csneg_cmp(int x)
     x = -x;
   return x;
 }
+
+unsigned long long
+test_csneg_uxtw (unsigned int a,
+		 unsigned int b,
+		 unsigned int c)
+{
+  /* { dg-final { scan-assembler "csneg\tw\[0-9\]*.*ne" } } */
+  /* { dg-final { scan-assembler-not "uxtw\tw\[0-9\]*.*" } } */
+  unsigned int val;
+  val = a ? b: -c;
+  return val;
+}