From: Segher Boessenkool Date: Sun, 17 Aug 2014 23:39:53 +0000 (+0200) Subject: constraints.md ("S"): Require TARGET_POWERPC64. X-Git-Tag: releases/gcc-5.1.0~5427 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=44c3a8bb733c1ecee2f5fa97d8b16331c30b37de;p=thirdparty%2Fgcc.git constraints.md ("S"): Require TARGET_POWERPC64. 2014-08-17 Segher Boessenkool * config/rs6000/constraints.md ("S"): Require TARGET_POWERPC64. * config/rs6000/htm.md (ttest): Remove clobber. * config/rs6000/predicates.md (any_mask_operand): New predicate. (and_operand): Reformat. (and_2rld_operand): New predicate. * config/rs6000/rs6000-protos.h (rs6000_split_logical): Remove last parameter. * config/rs6000/rs6000.c (rs6000_split_logical_inner): Remove last parameter. Handle AND directly. (rs6000_split_logical_di): Remove last parameter. (rs6000_split_logical): Remove last parameter. Remove obsolete comment. * config/rs6000/rs6000.md (BOOL_REGS_AND_CR0): Delete. (one_cmpl2): Adjust call of rs6000_split_logical. (ctz2, ffs2): Delete clobber. Reformat. (andsi3, andsi3_mc, andsi3_nomc, *andsi3_internal2_mc, *andsi3_internal3_mc, *andsi3_internal4, *andsi3_internal5_mc, and 5 anonymous splitters): Delete. (and3): New expander. (*and3, *and3_dot, *and3_dot2): New. (and3_imm, *and3_imm_dot, *and3_imm_dot2): New. (*and3_mask, *and3_mask_dot, *and3_mask_dot2): New. (ior, xor3): Adjust call of rs6000_split_logical. (floatdisf2_internal1): Remove clobbers. (anddi3, anddi3_mc, anddi3_nomc, anddi3_internal2_mc, *anddi3_internal3_mc, and 4 anonymous splitters): Delete. (*anddi3_2rld, *anddi3_2rld_dot, *anddi3_2rld_dot2): New. (and3 for BOOL_128): Remove clobber. (*and3_internal for BOOL_128): Remove clobber. Adjust call of rs6000_split_logical. (*bool3_internal for BOOL_128): Adjust call of rs6000_split_logical. (*boolc3_internal1 for BOOL_128, *boolc3_internal2 for BOOL_128, *boolcc3_internal1 for BOOL_128, *boolcc3_internal2 for BOOL_128, *eqv3_internal1 for BOOL_128, *eqv3_internal2 for BOOL_128, *one_cmpl3_internal for BOOL_128): Ditto. * config/rs6000/vector.md (*vec_reload_and_plus_): Delete. From-SVN: r214080 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index bf1dfd68f47d..c70d519bc294 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,48 @@ +2014-08-17 Segher Boessenkool + + * config/rs6000/constraints.md ("S"): Require TARGET_POWERPC64. + * config/rs6000/htm.md (ttest): Remove clobber. + * config/rs6000/predicates.md (any_mask_operand): New predicate. + (and_operand): Reformat. + (and_2rld_operand): New predicate. + * config/rs6000/rs6000-protos.h (rs6000_split_logical): Remove last + parameter. + * config/rs6000/rs6000.c (rs6000_split_logical_inner): Remove last + parameter. Handle AND directly. + (rs6000_split_logical_di): Remove last parameter. + (rs6000_split_logical): Remove last parameter. Remove obsolete + comment. + * config/rs6000/rs6000.md (BOOL_REGS_AND_CR0): Delete. + (one_cmpl2): Adjust call of rs6000_split_logical. + (ctz2, ffs2): Delete clobber. Reformat. + (andsi3, andsi3_mc, andsi3_nomc, *andsi3_internal2_mc, + *andsi3_internal3_mc, *andsi3_internal4, *andsi3_internal5_mc, + and 5 anonymous splitters): Delete. + (and3): New expander. + (*and3, *and3_dot, *and3_dot2): New. + (and3_imm, *and3_imm_dot, *and3_imm_dot2): New. + (*and3_mask, *and3_mask_dot, *and3_mask_dot2): New. + (ior, xor3): Adjust call of rs6000_split_logical. + (floatdisf2_internal1): Remove clobbers. + (anddi3, anddi3_mc, anddi3_nomc, anddi3_internal2_mc, + *anddi3_internal3_mc, and 4 anonymous splitters): Delete. + (*anddi3_2rld, *anddi3_2rld_dot, *anddi3_2rld_dot2): New. + (and3 for BOOL_128): Remove clobber. + (*and3_internal for BOOL_128): Remove clobber. Adjust call of + rs6000_split_logical. + (*bool3_internal for BOOL_128): Adjust call of + rs6000_split_logical. + (*boolc3_internal1 for BOOL_128, + *boolc3_internal2 for BOOL_128, + *boolcc3_internal1 for BOOL_128, + *boolcc3_internal2 for BOOL_128, + *eqv3_internal1 for BOOL_128, + *eqv3_internal2 for BOOL_128, + *one_cmpl3_internal for BOOL_128): Ditto. + * config/rs6000/vector.md (*vec_reload_and_plus_): Delete. + 2014-08-17 Segher Boessenkool * config/rs6000/rs6000.md (*boolccsi3_internal1, *boolccsi3_internal2 diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index 0385f3c7f92d..5ac71ac2e996 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -232,7 +232,8 @@ usually better to use @samp{m} or @samp{es} in @code{asm} statements)" (define_constraint "S" "Constant that can be placed into a 64-bit mask operand" - (match_operand 0 "mask64_operand")) + (and (match_test "TARGET_POWERPC64") + (match_operand 0 "mask64_operand"))) (define_constraint "T" "Constant that can be placed into a 32-bit mask operand" diff --git a/gcc/config/rs6000/htm.md b/gcc/config/rs6000/htm.md index ca7f7fdf4fb7..140212b42187 100644 --- a/gcc/config/rs6000/htm.md +++ b/gcc/config/rs6000/htm.md @@ -180,9 +180,9 @@ UNSPECV_HTM_TABORTWCI)) (set (subreg:CC (match_dup 2) 0) (match_dup 1)) (set (match_dup 3) (lshiftrt:SI (match_dup 2) (const_int 28))) - (parallel [(set (match_operand:SI 0 "int_reg_operand" "") - (and:SI (match_dup 3) (const_int 15))) - (clobber (scratch:CC))])] + (set (match_operand:SI 0 "int_reg_operand" "") + (and:SI (match_dup 3) + (const_int 15)))] "TARGET_HTM" { operands[1] = gen_rtx_REG (CCmode, CR0_REGNO); diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index f538b422e8ec..0c5b9961f030 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -940,6 +940,12 @@ return c == -lsb; }) +;; Match a mask_operand or a mask64_operand. +(define_predicate "any_mask_operand" + (ior (match_operand 0 "mask_operand") + (and (match_test "TARGET_POWERPC64 && mode == DImode") + (match_operand 0 "mask64_operand")))) + ;; Like and_operand, but also match constants that can be implemented ;; with two rldicl or rldicr insns. (define_predicate "and64_2_operand" @@ -952,11 +958,18 @@ ;; constant that can be used as the operand of a logical AND. (define_predicate "and_operand" (ior (match_operand 0 "mask_operand") - (ior (and (match_test "TARGET_POWERPC64 && mode == DImode") - (match_operand 0 "mask64_operand")) - (if_then_else (match_test "fixed_regs[CR0_REGNO]") - (match_operand 0 "gpc_reg_operand") - (match_operand 0 "logical_operand"))))) + (and (match_test "TARGET_POWERPC64 && mode == DImode") + (match_operand 0 "mask64_operand")) + (if_then_else (match_test "fixed_regs[CR0_REGNO]") + (match_operand 0 "gpc_reg_operand") + (match_operand 0 "logical_operand")))) + +;; Return 1 if the operand is a constant that can be used as the operand +;; of a logical AND, implemented with two rld* insns, and it cannot be done +;; using just one insn. +(define_predicate "and_2rld_operand" + (and (match_operand 0 "and64_2_operand") + (not (match_operand 0 "and_operand")))) ;; Return 1 if the operand is either a logical operand or a short cint operand. (define_predicate "scc_eq_operand" diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index 82564db5c905..abe29d5b1e4d 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -150,7 +150,7 @@ extern rtx rs6000_address_for_fpconvert (rtx); extern rtx rs6000_address_for_altivec (rtx); extern rtx rs6000_allocate_stack_temp (enum machine_mode, bool, bool); extern int rs6000_loop_align (rtx); -extern void rs6000_split_logical (rtx [], enum rtx_code, bool, bool, bool, rtx); +extern void rs6000_split_logical (rtx [], enum rtx_code, bool, bool, bool); #endif /* RTX_CODE */ #ifdef TREE_CODE diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 9821c6bc4d04..ec4e16325b0d 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -32795,9 +32795,7 @@ rs6000_set_up_by_prologue (struct hard_reg_set_container *set) MODE is the machine mode. If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT. If COMPLEMENT_OP1_P is true, wrap operand1 with NOT. - If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. - CLOBBER_REG is either NULL or a scratch register of type CC to allow - formation of the AND instructions. */ + If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */ static void rs6000_split_logical_inner (rtx dest, @@ -32807,11 +32805,9 @@ rs6000_split_logical_inner (rtx dest, enum machine_mode mode, bool complement_final_p, bool complement_op1_p, - bool complement_op2_p, - rtx clobber_reg) + bool complement_op2_p) { rtx bool_rtx; - rtx set_rtx; /* Optimize AND of 0/0xffffffff and IOR/XOR of 0. */ if (op2 && GET_CODE (op2) == CONST_INT @@ -32851,6 +32847,13 @@ rs6000_split_logical_inner (rtx dest, } } + if (code == AND && mode == SImode + && !complement_final_p && !complement_op1_p && !complement_op2_p) + { + emit_insn (gen_andsi3 (dest, op1, op2)); + return; + } + if (complement_op1_p) op1 = gen_rtx_NOT (mode, op1); @@ -32864,17 +32867,7 @@ rs6000_split_logical_inner (rtx dest, if (complement_final_p) bool_rtx = gen_rtx_NOT (mode, bool_rtx); - set_rtx = gen_rtx_SET (VOIDmode, dest, bool_rtx); - - /* Is this AND with an explicit clobber? */ - if (clobber_reg) - { - rtx clobber = gen_rtx_CLOBBER (VOIDmode, clobber_reg); - set_rtx = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set_rtx, clobber)); - } - - emit_insn (set_rtx); - return; + emit_insn (gen_rtx_SET (VOIDmode, dest, bool_rtx)); } /* Split a DImode AND/IOR/XOR with a constant on a 32-bit system. These @@ -32895,8 +32888,7 @@ rs6000_split_logical_di (rtx operands[3], enum rtx_code code, bool complement_final_p, bool complement_op1_p, - bool complement_op2_p, - rtx clobber_reg) + bool complement_op2_p) { const HOST_WIDE_INT lower_32bits = HOST_WIDE_INT_C(0xffffffff); const HOST_WIDE_INT upper_32bits = ~ lower_32bits; @@ -32957,7 +32949,6 @@ rs6000_split_logical_di (rtx operands[3], && !complement_final_p && !complement_op1_p && !complement_op2_p - && clobber_reg == NULL_RTX && !logical_const_operand (op2_hi_lo[i], SImode)) { HOST_WIDE_INT value = INTVAL (op2_hi_lo[i]); @@ -32970,18 +32961,15 @@ rs6000_split_logical_di (rtx operands[3], hi_16bits |= upper_32bits; rs6000_split_logical_inner (tmp, op1_hi_lo[i], GEN_INT (hi_16bits), - code, SImode, false, false, false, - NULL_RTX); + code, SImode, false, false, false); rs6000_split_logical_inner (op0_hi_lo[i], tmp, GEN_INT (lo_16bits), - code, SImode, false, false, false, - NULL_RTX); + code, SImode, false, false, false); } else rs6000_split_logical_inner (op0_hi_lo[i], op1_hi_lo[i], op2_hi_lo[i], code, SImode, complement_final_p, - complement_op1_p, complement_op2_p, - clobber_reg); + complement_op1_p, complement_op2_p); } return; @@ -32993,20 +32981,16 @@ rs6000_split_logical_di (rtx operands[3], OPERANDS is an array containing the destination and two input operands. CODE is the base operation (AND, IOR, XOR, NOT). - MODE is the machine mode. If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT. If COMPLEMENT_OP1_P is true, wrap operand1 with NOT. - If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. - CLOBBER_REG is either NULL or a scratch register of type CC to allow - formation of the AND instructions. */ + If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */ void rs6000_split_logical (rtx operands[3], enum rtx_code code, bool complement_final_p, bool complement_op1_p, - bool complement_op2_p, - rtx clobber_reg) + bool complement_op2_p) { enum machine_mode mode = GET_MODE (operands[0]); enum machine_mode sub_mode; @@ -33018,8 +33002,7 @@ rs6000_split_logical (rtx operands[3], if (mode == DImode && !TARGET_POWERPC64) { rs6000_split_logical_di (operands, code, complement_final_p, - complement_op1_p, complement_op2_p, - clobber_reg); + complement_op1_p, complement_op2_p); return; } @@ -33052,7 +33035,7 @@ rs6000_split_logical (rtx operands[3], rs6000_split_logical_inner (sub_op0, sub_op1, sub_op2, code, sub_mode, complement_final_p, complement_op1_p, - complement_op2_p, clobber_reg); + complement_op2_p); } return; diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index b6258310c7ac..2d1033cbce66 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -551,19 +551,6 @@ (V2DI "wa,v,r,0,0") (V2DF "wa,v,r,0,0") (V1TI "wa,v,r,0,0")]) - -;; Mode attribute for the clobber of CC0 for AND expansion. -;; For the 128-bit types, we never do AND immediate, but we need to -;; get the correct number of X's for the number of operands. -(define_mode_attr BOOL_REGS_AND_CR0 [(TI "X,X,X,X,X") - (PTI "X,X,X") - (V16QI "X,X,X,X,X") - (V8HI "X,X,X,X,X") - (V4SI "X,X,X,X,X") - (V4SF "X,X,X,X,X") - (V2DI "X,X,X,X,X") - (V2DF "X,X,X,X,X") - (V1TI "X,X,X,X,X")]) ;; Start with fixed-point load and store insns. Here we put only the more ;; complex forms. Basic data transfer is done later. @@ -1956,7 +1943,7 @@ { if (mode == DImode && !TARGET_POWERPC64) { - rs6000_split_logical (operands, NOT, false, false, false, NULL_RTX); + rs6000_split_logical (operands, NOT, false, false, false); DONE; } }) @@ -2185,12 +2172,14 @@ (define_expand "ctz2" [(set (match_dup 2) (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" ""))) - (parallel [(set (match_dup 3) (and:GPR (match_dup 1) - (match_dup 2))) - (clobber (scratch:CC))]) - (set (match_dup 4) (clz:GPR (match_dup 3))) + (set (match_dup 3) + (and:GPR (match_dup 1) + (match_dup 2))) + (set (match_dup 4) + (clz:GPR (match_dup 3))) (set (match_operand:GPR 0 "gpc_reg_operand" "") - (minus:GPR (match_dup 5) (match_dup 4)))] + (minus:GPR (match_dup 5) + (match_dup 4)))] "" { operands[2] = gen_reg_rtx (mode); @@ -2202,12 +2191,14 @@ (define_expand "ffs2" [(set (match_dup 2) (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" ""))) - (parallel [(set (match_dup 3) (and:GPR (match_dup 1) - (match_dup 2))) - (clobber (scratch:CC))]) - (set (match_dup 4) (clz:GPR (match_dup 3))) + (set (match_dup 3) + (and:GPR (match_dup 1) + (match_dup 2))) + (set (match_dup 4) + (clz:GPR (match_dup 3))) (set (match_operand:GPR 0 "gpc_reg_operand" "") - (minus:GPR (match_dup 5) (match_dup 4)))] + (minus:GPR (match_dup 5) + (match_dup 4)))] "" { operands[2] = gen_reg_rtx (mode); @@ -2919,221 +2910,226 @@ ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all ;; those rotate-and-mask operations. Thus, the AND insns come first. -(define_expand "andsi3" - [(parallel - [(set (match_operand:SI 0 "gpc_reg_operand" "") - (and:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "and_operand" ""))) - (clobber (match_scratch:CC 3 ""))])] +(define_expand "and3" + [(set (match_operand:SDI 0 "gpc_reg_operand" "") + (and:SDI (match_operand:SDI 1 "gpc_reg_operand" "") + (match_operand:SDI 2 "reg_or_cint_operand" "")))] "" - "") - -(define_insn "andsi3_mc" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") - (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") - (match_operand:SI 2 "and_operand" "?r,T,K,L"))) - (clobber (match_scratch:CC 3 "=X,X,x,x"))] - "rs6000_gen_cell_microcode" - "@ - and %0,%1,%2 - rlwinm %0,%1,0,%m2,%M2 - andi. %0,%1,%b2 - andis. %0,%1,%u2" - [(set_attr "type" "*,shift,logical,logical") - (set_attr "dot" "no,no,yes,yes")]) +{ + if (mode == DImode && !TARGET_POWERPC64) + { + rs6000_split_logical (operands, AND, false, false, false); + DONE; + } -(define_insn "andsi3_nomc" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") - (match_operand:SI 2 "and_operand" "?r,T"))) - (clobber (match_scratch:CC 3 "=X,X"))] - "!rs6000_gen_cell_microcode" - "@ - and %0,%1,%2 - rlwinm %0,%1,0,%m2,%M2" - [(set_attr "type" "logical,shift")]) + if (logical_const_operand (operands[2], mode) + && !any_mask_operand (operands[2], mode)) + { + emit_insn (gen_and3_imm (operands[0], operands[1], operands[2])); + DONE; + } -(define_insn "andsi3_internal0_nomc" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") - (match_operand:SI 2 "and_operand" "?r,T")))] - "!rs6000_gen_cell_microcode" - "@ - and %0,%1,%2 - rlwinm %0,%1,0,%m2,%M2" - [(set_attr "type" "logical,shift")]) + if ((mode == DImode && !and64_2_operand (operands[2], mode)) + || (mode != DImode && !and_operand (operands[2], mode))) + operands[2] = force_reg (mode, operands[2]); +}) -;; Note to set cr's other than cr0 we do the and immediate and then -;; the test again -- this avoids a mfcr which on the higher end -;; machines causes an execution serialization +(define_insn "*and3" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand:GPR 2 "gpc_reg_operand" "r")))] + "" + "and %0,%1,%2" + [(set_attr "type" "logical")]) -(define_insn "*andsi3_internal2_mc" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") - (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") - (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) +(define_insn_and_split "*and3_dot" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:GPR 2 "gpc_reg_operand" "r,r")) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) - (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] - "TARGET_32BIT && rs6000_gen_cell_microcode" + (clobber (match_scratch:GPR 0 "=r,r"))] + "mode == Pmode && rs6000_gen_cell_microcode" "@ - and. %3,%1,%2 - andi. %3,%1,%b2 - andis. %3,%1,%u2 - rlwinm. %3,%1,0,%m2,%M2 - # - # - # + and. %0,%1,%2 #" - [(set_attr "type" "logical,logical,logical,shift,\ - compare,compare,compare,compare") + "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)" + [(set (match_dup 0) + (and:GPR (match_dup 1) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "" + [(set_attr "type" "logical") (set_attr "dot" "yes") - (set_attr "length" "4,4,4,4,8,8,8,8")]) + (set_attr "length" "4,8")]) -(define_insn "*andsi3_internal3_mc" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") - (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") - (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) +(define_insn_and_split "*and3_dot2" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:GPR 2 "gpc_reg_operand" "r,r")) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) - (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] - "TARGET_64BIT && rs6000_gen_cell_microcode" + (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") + (and:GPR (match_dup 1) + (match_dup 2)))] + "mode == Pmode && rs6000_gen_cell_microcode" "@ - # - andi. %3,%1,%b2 - andis. %3,%1,%u2 - rlwinm. %3,%1,0,%m2,%M2 - # - # - # + and. %0,%1,%2 #" - [(set_attr "type" "compare,logical,logical,shift,compare,\ - compare,compare,compare") + "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)" + [(set (match_dup 0) + (and:GPR (match_dup 1) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "" + [(set_attr "type" "logical") (set_attr "dot" "yes") - (set_attr "length" "8,4,4,4,8,8,8,8")]) + (set_attr "length" "4,8")]) -(define_split - [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "") - (match_operand:GPR 2 "and_operand" "")) - (const_int 0))) - (clobber (match_scratch:GPR 3 "")) - (clobber (match_scratch:CC 4 ""))] - "reload_completed" - [(parallel [(set (match_dup 3) - (and: (match_dup 1) - (match_dup 2))) - (clobber (match_dup 4))]) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") -;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the -;; whole 64 bit reg, and we don't know what is in the high 32 bits. +(define_insn "and3_imm" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r") + (match_operand:GPR 2 "logical_const_operand" "n"))) + (clobber (match_scratch:CC 3 "=x"))] + "rs6000_gen_cell_microcode + && !any_mask_operand (operands[2], mode)" + "andi%e2. %0,%1,%u2" + [(set_attr "type" "logical") + (set_attr "dot" "yes")]) -(define_split - [(set (match_operand:CC 0 "cc_reg_operand" "") - (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "gpc_reg_operand" "")) +(define_insn_and_split "*and3_imm_dot" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y") + (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r") + (match_operand:GPR 2 "logical_const_operand" "n,n")) (const_int 0))) - (clobber (match_scratch:SI 3 "")) - (clobber (match_scratch:CC 4 ""))] - "TARGET_POWERPC64 && reload_completed" - [(parallel [(set (match_dup 3) - (and:SI (match_dup 1) - (match_dup 2))) + (clobber (match_scratch:GPR 0 "=r,r")) + (clobber (match_scratch:CC 4 "=X,x"))] + "(mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff) + && rs6000_gen_cell_microcode" + "@ + andi%e2. %0,%1,%u2 + #" + "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)" + [(parallel [(set (match_dup 0) + (and:GPR (match_dup 1) + (match_dup 2))) (clobber (match_dup 4))]) - (set (match_dup 0) - (compare:CC (match_dup 3) + (set (match_dup 3) + (compare:CC (match_dup 0) (const_int 0)))] - "") + "" + [(set_attr "type" "logical") + (set_attr "dot" "yes") + (set_attr "length" "4,8")]) -(define_insn "*andsi3_internal4" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") - (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") - (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) +(define_insn_and_split "*and3_imm_dot2" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y") + (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r") + (match_operand:GPR 2 "logical_const_operand" "n,n")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") - (and:SI (match_dup 1) - (match_dup 2))) - (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] - "TARGET_32BIT && rs6000_gen_cell_microcode" + (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") + (and:GPR (match_dup 1) + (match_dup 2))) + (clobber (match_scratch:CC 4 "=X,x"))] + "(mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff) + && rs6000_gen_cell_microcode" "@ - and. %0,%1,%2 - andi. %0,%1,%b2 - andis. %0,%1,%u2 - rlwinm. %0,%1,0,%m2,%M2 - # - # - # + andi%e2. %0,%1,%u2 #" - [(set_attr "type" "logical,logical,logical,shift,\ - compare,compare,compare,compare") + "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)" + [(parallel [(set (match_dup 0) + (and:GPR (match_dup 1) + (match_dup 2))) + (clobber (match_dup 4))]) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "" + [(set_attr "type" "logical") (set_attr "dot" "yes") - (set_attr "length" "4,4,4,4,8,8,8,8")]) + (set_attr "length" "4,8")]) -(define_insn "*andsi3_internal5_mc" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") - (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") - (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) + +(define_insn "*and3_mask" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") + (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r") + (match_operand:GPR 2 "any_mask_operand" "S,T")))] + "" + "@ + rldic%B2 %0,%1,0,%S2 + rlwinm %0,%1,0,%m2,%M2" + [(set_attr "type" "shift")]) + +(define_insn_and_split "*and3_mask_dot" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") + (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r") + (match_operand:GPR 2 "any_mask_operand" "S,T,S,T")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") - (and:SI (match_dup 1) - (match_dup 2))) - (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] - "TARGET_64BIT && rs6000_gen_cell_microcode" + (clobber (match_scratch:GPR 0 "=r,r,r,r"))] + "(mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff) + && rs6000_gen_cell_microcode + && !logical_const_operand (operands[2], mode)" "@ - # - andi. %0,%1,%b2 - andis. %0,%1,%u2 + rldic%B2. %0,%1,0,%S2 rlwinm. %0,%1,0,%m2,%M2 # - # - # #" - [(set_attr "type" "compare,logical,logical,shift,compare,\ - compare,compare,compare") - (set_attr "dot" "yes") - (set_attr "length" "8,4,4,4,8,8,8,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "and_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (and:SI (match_dup 1) - (match_dup 2))) - (clobber (match_scratch:CC 4 ""))] - "reload_completed" - [(parallel [(set (match_dup 0) - (and:SI (match_dup 1) - (match_dup 2))) - (clobber (match_dup 4))]) + "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)" + [(set (match_dup 0) + (and:GPR (match_dup 1) + (match_dup 2))) (set (match_dup 3) (compare:CC (match_dup 0) (const_int 0)))] - "") + "" + [(set_attr "type" "shift") + (set_attr "dot" "yes") + (set_attr "length" "4,4,8,8")]) -(define_split - [(set (match_operand:CC 3 "cc_reg_operand" "") - (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "gpc_reg_operand" "")) +(define_insn_and_split "*and3_mask_dot2" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") + (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r") + (match_operand:GPR 2 "any_mask_operand" "S,T,S,T")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (and:SI (match_dup 1) - (match_dup 2))) - (clobber (match_scratch:CC 4 ""))] - "TARGET_POWERPC64 && reload_completed" - [(parallel [(set (match_dup 0) - (and:SI (match_dup 1) - (match_dup 2))) - (clobber (match_dup 4))]) + (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r") + (and:GPR (match_dup 1) + (match_dup 2)))] + "(mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff) + && rs6000_gen_cell_microcode + && !logical_const_operand (operands[2], mode)" + "@ + rldic%B2. %0,%1,0,%S2 + rlwinm. %0,%1,0,%m2,%M2 + # + #" + "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)" + [(set (match_dup 0) + (and:GPR (match_dup 1) + (match_dup 2))) (set (match_dup 3) (compare:CC (match_dup 0) (const_int 0)))] - "") + "" + [(set_attr "type" "shift") + (set_attr "dot" "yes") + (set_attr "length" "4,4,8,8")]) + + + +(define_insn "andsi3_internal0_nomc" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") + (match_operand:SI 2 "and_operand" "?r,T")))] + "!rs6000_gen_cell_microcode" + "@ + and %0,%1,%2 + rlwinm %0,%1,0,%m2,%M2" + [(set_attr "type" "logical,shift")]) + ;; Handle the PowerPC64 rlwinm corner case @@ -3168,7 +3164,7 @@ { if (mode == DImode && !TARGET_POWERPC64) { - rs6000_split_logical (operands, IOR, false, false, false, NULL_RTX); + rs6000_split_logical (operands, IOR, false, false, false); DONE; } @@ -3198,7 +3194,7 @@ { if (mode == DImode && !TARGET_POWERPC64) { - rs6000_split_logical (operands, XOR, false, false, false, NULL_RTX); + rs6000_split_logical (operands, XOR, false, false, false); DONE; } @@ -6479,9 +6475,8 @@ (define_expand "floatdisf2_internal2" [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "") (const_int 53))) - (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1) - (const_int 2047))) - (clobber (scratch:CC))]) + (set (match_operand:DI 0 "" "") (and:DI (match_dup 1) + (const_int 2047))) (set (match_dup 3) (plus:DI (match_dup 3) (const_int 1))) (set (match_dup 0) (plus:DI (match_dup 0) @@ -6490,9 +6485,8 @@ (const_int 2))) (set (match_dup 0) (ior:DI (match_dup 0) (match_dup 1))) - (parallel [(set (match_dup 0) (and:DI (match_dup 0) - (const_int -2048))) - (clobber (scratch:CC))]) + (set (match_dup 0) (and:DI (match_dup 0) + (const_int -2048))) (set (pc) (if_then_else (geu (match_dup 4) (const_int 0)) (label_ref (match_operand:DI 2 "" "")) (pc))) @@ -7627,64 +7621,14 @@ (const_int 0)))] "") -(define_expand "anddi3" - [(parallel - [(set (match_operand:DI 0 "gpc_reg_operand" "") - (and:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "reg_or_cint_operand" ""))) - (clobber (match_scratch:CC 3 ""))])] - "" -{ - if (!TARGET_POWERPC64) - { - rtx cc = gen_rtx_SCRATCH (CCmode); - rs6000_split_logical (operands, AND, false, false, false, cc); - DONE; - } - else if (!and64_2_operand (operands[2], DImode)) - operands[2] = force_reg (DImode, operands[2]); -}) - -(define_insn "anddi3_mc" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r") - (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r") - (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t"))) - (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))] - "TARGET_POWERPC64 && rs6000_gen_cell_microcode" - "@ - and %0,%1,%2 - rldic%B2 %0,%1,0,%S2 - rlwinm %0,%1,0,%m2,%M2 - andi. %0,%1,%b2 - andis. %0,%1,%u2 - #" - [(set_attr "type" "*,shift,shift,logical,logical,*") - (set_attr "dot" "no,no,no,yes,yes,no") - (set_attr "length" "4,4,4,4,4,8")]) - -(define_insn "anddi3_nomc" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") - (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") - (match_operand:DI 2 "and64_2_operand" "?r,S,T,t"))) - (clobber (match_scratch:CC 3 "=X,X,X,X"))] - "TARGET_POWERPC64 && !rs6000_gen_cell_microcode" - "@ - and %0,%1,%2 - rldic%B2 %0,%1,0,%S2 - rlwinm %0,%1,0,%m2,%M2 - #" - [(set_attr "type" "*,shift,shift,*") - (set_attr "length" "4,4,4,8")]) -(define_split - [(set (match_operand:DI 0 "gpc_reg_operand" "") - (and:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "mask64_2_operand" ""))) - (clobber (match_scratch:CC 3 ""))] - "TARGET_POWERPC64 - && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) - && !mask_operand (operands[2], DImode) - && !mask64_operand (operands[2], DImode)" +(define_insn_and_split "*anddi3_2rld" + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") + (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r") + (match_operand:DI 2 "and_2rld_operand" "n")))] + "TARGET_POWERPC64" + "#" + "" [(set (match_dup 0) (and:DI (rotate:DI (match_dup 1) (match_dup 4)) @@ -7695,144 +7639,76 @@ (match_dup 7)))] { build_mask64_2_operands (operands[2], &operands[4]); -}) +} + [(set_attr "length" "8")]) -(define_insn "*anddi3_internal2_mc" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y") - (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r") - (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t")) +(define_insn_and_split "*anddi3_2rld_dot" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") + (match_operand:DI 2 "and_2rld_operand" "n,n")) (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r")) - (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))] + (clobber (match_scratch:DI 0 "=r,r"))] "TARGET_64BIT && rs6000_gen_cell_microcode" "@ - and. %3,%1,%2 - rldic%B2. %3,%1,0,%S2 - rlwinm. %3,%1,0,%m2,%M2 - andi. %3,%1,%b2 - andis. %3,%1,%u2 - # - # - # - # - # # #" - [(set_attr "type" "logical,shift,shift,logical,\ - logical,compare,compare,compare,compare,compare,\ - compare,compare") - (set_attr "dot" "yes") - (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_operand" "") - (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "mask64_2_operand" "")) - (const_int 0))) - (clobber (match_scratch:DI 3 "")) - (clobber (match_scratch:CC 4 ""))] - "TARGET_64BIT && reload_completed - && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) - && !mask_operand (operands[2], DImode) - && !mask64_operand (operands[2], DImode)" - [(set (match_dup 3) + "&& reload_completed" + [(set (match_dup 0) (and:DI (rotate:DI (match_dup 1) - (match_dup 5)) - (match_dup 6))) - (parallel [(set (match_dup 0) - (compare:CC (and:DI (rotate:DI (match_dup 3) - (match_dup 7)) - (match_dup 8)) + (match_dup 4)) + (match_dup 5))) + (parallel [(set (match_dup 3) + (compare:CC (and:DI (rotate:DI (match_dup 0) + (match_dup 6)) + (match_dup 7)) (const_int 0))) - (clobber (match_dup 3))])] - " + (clobber (match_dup 0))])] { - build_mask64_2_operands (operands[2], &operands[5]); -}") + build_mask64_2_operands (operands[2], &operands[4]); +} + [(set_attr "type" "compare") + (set_attr "dot" "yes") + (set_attr "length" "8,12")]) -(define_insn "*anddi3_internal3_mc" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y") - (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r") - (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t")) +(define_insn_and_split "*anddi3_2rld_dot2" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") + (match_operand:DI 2 "and_2rld_operand" "n,n")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r") - (and:DI (match_dup 1) (match_dup 2))) - (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))] + (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + (and:DI (match_dup 1) + (match_dup 2)))] "TARGET_64BIT && rs6000_gen_cell_microcode" "@ - and. %0,%1,%2 - rldic%B2. %0,%1,0,%S2 - rlwinm. %0,%1,0,%m2,%M2 - andi. %0,%1,%b2 - andis. %0,%1,%u2 - # - # - # - # - # # #" - [(set_attr "type" "logical,shift,shift,logical,\ - logical,compare,compare,compare,compare,compare,\ - compare,compare") - (set_attr "dot" "yes") - (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "and64_2_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (and:DI (match_dup 1) (match_dup 2))) - (clobber (match_scratch:CC 4 ""))] - "TARGET_64BIT && reload_completed" - [(parallel [(set (match_dup 0) - (and:DI (match_dup 1) (match_dup 2))) - (clobber (match_dup 4))]) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - -(define_split - [(set (match_operand:CC 3 "cc_reg_operand" "") - (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "mask64_2_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (and:DI (match_dup 1) (match_dup 2))) - (clobber (match_scratch:CC 4 ""))] - "TARGET_64BIT && reload_completed - && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) - && !mask_operand (operands[2], DImode) - && !mask64_operand (operands[2], DImode)" + "&& reload_completed" [(set (match_dup 0) (and:DI (rotate:DI (match_dup 1) - (match_dup 5)) - (match_dup 6))) + (match_dup 4)) + (match_dup 5))) (parallel [(set (match_dup 3) (compare:CC (and:DI (rotate:DI (match_dup 0) - (match_dup 7)) - (match_dup 8)) + (match_dup 6)) + (match_dup 7)) (const_int 0))) (set (match_dup 0) (and:DI (rotate:DI (match_dup 0) - (match_dup 7)) - (match_dup 8)))])] - " + (match_dup 6)) + (match_dup 7)))])] { - build_mask64_2_operands (operands[2], &operands[5]); -}") + build_mask64_2_operands (operands[2], &operands[4]); +} + [(set_attr "type" "compare") + (set_attr "dot" "yes") + (set_attr "length" "8,12")]) ;; 128-bit logical operations expanders (define_expand "and3" - [(parallel [(set (match_operand:BOOL_128 0 "vlogical_operand" "") - (and:BOOL_128 - (match_operand:BOOL_128 1 "vlogical_operand" "") - (match_operand:BOOL_128 2 "vlogical_operand" ""))) - (clobber (match_scratch:CC 3 ""))])] + [(set (match_operand:BOOL_128 0 "vlogical_operand" "") + (and:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "") + (match_operand:BOOL_128 2 "vlogical_operand" "")))] "" "") @@ -7905,8 +7781,7 @@ [(set (match_operand:BOOL_128 0 "vlogical_operand" "=") (and:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "%") - (match_operand:BOOL_128 2 "vlogical_operand" ""))) - (clobber (match_scratch:CC 3 ""))] + (match_operand:BOOL_128 2 "vlogical_operand" "")))] "" { if (TARGET_VSX && vsx_register_operand (operands[0], mode)) @@ -7920,7 +7795,7 @@ "reload_completed && int_reg_operand (operands[0], mode)" [(const_int 0)] { - rs6000_split_logical (operands, AND, false, false, false, operands[3]); + rs6000_split_logical (operands, AND, false, false, false); DONE; } [(set (attr "type") @@ -7956,8 +7831,7 @@ "reload_completed && int_reg_operand (operands[0], mode)" [(const_int 0)] { - rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, false, - NULL_RTX); + rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, false); DONE; } [(set (attr "type") @@ -7995,8 +7869,7 @@ && reload_completed && int_reg_operand (operands[0], mode)" [(const_int 0)] { - rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false, - NULL_RTX); + rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false); DONE; } [(set (attr "type") @@ -8024,8 +7897,7 @@ "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)" [(const_int 0)] { - rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false, - NULL_RTX); + rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false); DONE; } [(set_attr "type" "integer") @@ -8057,8 +7929,7 @@ && reload_completed && int_reg_operand (operands[0], mode)" [(const_int 0)] { - rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true, - NULL_RTX); + rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true); DONE; } [(set (attr "type") @@ -8087,8 +7958,7 @@ "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)" [(const_int 0)] { - rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true, - NULL_RTX); + rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true); DONE; } [(set_attr "type" "integer") @@ -8117,7 +7987,7 @@ && int_reg_operand (operands[0], mode)" [(const_int 0)] { - rs6000_split_logical (operands, XOR, true, false, false, NULL_RTX); + rs6000_split_logical (operands, XOR, true, false, false); DONE; } [(set (attr "type") @@ -8145,7 +8015,7 @@ "reload_completed && !TARGET_P8_VECTOR" [(const_int 0)] { - rs6000_split_logical (operands, XOR, true, false, false, NULL_RTX); + rs6000_split_logical (operands, XOR, true, false, false); DONE; } [(set_attr "type" "integer") @@ -8173,7 +8043,7 @@ "reload_completed && int_reg_operand (operands[0], mode)" [(const_int 0)] { - rs6000_split_logical (operands, NOT, false, false, false, NULL_RTX); + rs6000_split_logical (operands, NOT, false, false, false); DONE; } [(set (attr "type") diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index edbb83161d14..bfae244b497c 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -224,25 +224,9 @@ [(set (match_dup 0) (plus:P (match_dup 1) (match_dup 2))) - (parallel [(set (match_dup 0) - (and:P (match_dup 0) - (const_int -16))) - (clobber:CC (scratch:CC))])]) - -;; The normal ANDSI3/ANDDI3 won't match if reload decides to move an AND -16 -;; address to a register because there is no clobber of a (scratch), so we add -;; it here. -(define_insn_and_split "*vec_reload_and_reg_" - [(set (match_operand:P 0 "gpc_reg_operand" "=b") - (and:P (match_operand:P 1 "gpc_reg_operand" "r") - (const_int -16)))] - "(TARGET_ALTIVEC || TARGET_VSX) && (reload_in_progress || reload_completed)" - "#" - "&& reload_completed" - [(parallel [(set (match_dup 0) - (and:P (match_dup 1) - (const_int -16))) - (clobber:CC (scratch:CC))])]) + (set (match_dup 0) + (and:P (match_dup 0) + (const_int -16)))]) ;; Generic floating point vector arithmetic support (define_expand "add3"