From: Tejas Upadhyay Date: Wed, 14 Aug 2024 09:56:14 +0000 (+0530) Subject: drm/xe: Define STATELESS_COMPRESSION_CTRL as mcr register X-Git-Tag: v6.12-rc1~126^2~15^2~70 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=4551d60299b5ddc2655b6b365a4b92634e14e04f;p=thirdparty%2Fkernel%2Flinux.git drm/xe: Define STATELESS_COMPRESSION_CTRL as mcr register Register STATELESS_COMPRESSION_CTRL should be considered mcr register which should write to all slices as per documentation. Bspec: 71185 Fixes: ecabb5e6ce54 ("drm/xe/xe2: Add performance turning changes") Signed-off-by: Tejas Upadhyay Reviewed-by: Shekhar Chauhan Link: https://patchwork.freedesktop.org/patch/msgid/20240814095614.909774-4-tejas.upadhyay@intel.com Signed-off-by: Lucas De Marchi --- diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h index aeb17fcb27acc..0d1a4a9f4e119 100644 --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h @@ -80,7 +80,7 @@ #define LE_CACHEABILITY_MASK REG_GENMASK(1, 0) #define LE_CACHEABILITY(value) REG_FIELD_PREP(LE_CACHEABILITY_MASK, value) -#define STATELESS_COMPRESSION_CTRL XE_REG(0x4148) +#define STATELESS_COMPRESSION_CTRL XE_REG_MCR(0x4148) #define UNIFIED_COMPRESSION_FORMAT REG_GENMASK(3, 0) #define XE2_GAMREQSTRM_CTRL XE_REG_MCR(0x4194)