From: Frank Chang Date: Fri, 10 Dec 2021 07:57:02 +0000 (+0800) Subject: target/riscv: rvv-1.0: update opivv_vadc_check() comment X-Git-Tag: v7.0.0-rc0~121^2~4 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=45ca2ca6bdfbfc802fde87721ff3d164ea970d3d;p=thirdparty%2Fqemu.git target/riscv: rvv-1.0: update opivv_vadc_check() comment Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions is moved to Section 11.4 in RVV v1.0 spec. Update the comment, no functional changes. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-77-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 33ef7926e64..47eb3119cbe 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1613,7 +1613,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ /* * For vadc and vsbc, an illegal instruction exception is raised if the - * destination vector register is v0 and LMUL > 1. (Section 12.4) + * destination vector register is v0 and LMUL > 1. (Section 11.4) */ static bool opivv_vadc_check(DisasContext *s, arg_rmrr *a) {