From: Jeff Law <law@redhat.com>
Date: Wed, 25 Mar 2020 20:33:08 +0000 (-0600)
Subject:     Fix vector-compare-1 regressions on sh4/sh4eb caused by pattern clobbering T... 
X-Git-Tag: basepoints/gcc-11~694
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=48817fbd7616f086ac7bb1dd38b862f78762c9b8;p=thirdparty%2Fgcc.git

Fix vector-compare-1 regressions on sh4/sh4eb caused by pattern clobbering T reg without expressing that in its RTL.

            PR rtl-optimization/90275
            * config/sh/sh.md (mov_neg_si_t): Clobber the T register in the
            pattern.
---

diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md
index 4a1797160cf0..fc80278a395b 100644
--- a/gcc/config/sh/sh.md
+++ b/gcc/config/sh/sh.md
@@ -8395,9 +8395,15 @@
 ;; Store (negated) T bit as all zeros or ones in a reg.
 ;;	subc	Rn,Rn	! Rn = Rn - Rn - T; T = T
 ;;	not	Rn,Rn	! Rn = 0 - Rn
+;;
+;; Note the call to sh_split_treg_set_expr may clobber
+;; the T reg.  We must express this, even though it's
+;; not immediately obvious this pattern changes the
+;; T register.
 (define_insn_and_split "mov_neg_si_t"
   [(set (match_operand:SI 0 "arith_reg_dest" "=r")
-	(neg:SI (match_operand 1 "treg_set_expr")))]
+	(neg:SI (match_operand 1 "treg_set_expr")))
+   (clobber (reg:SI T_REG))]
   "TARGET_SH1"
 {
   gcc_assert (t_reg_operand (operands[1], VOIDmode));