From: Greg Kroah-Hartman Date: Sun, 15 Jan 2017 16:39:49 +0000 (+0100) Subject: 4.9-stable patches X-Git-Tag: v4.9.5~22 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=48962731c8a4534b6697cb26539e5021a4948129;p=thirdparty%2Fkernel%2Fstable-queue.git 4.9-stable patches added patches: drm-savage-dereferencing-an-error-pointer.patch drm-tegra-dpaux-fix-error-handling.patch drm-vc4-fix-a-couple-error-codes-in-vc4_cl_lookup_bos.patch input-i8042-add-pegatron-touchpad-to-noloop-table.patch input-xpad-use-correct-product-id-for-x360w-controllers.patch pinctrl-imx-fix-imx_pinctrl_desc-initialization.patch pinctrl-sh-pfc-r8a7795-use-lookup-function-for-bias-data.patch regulator-axp20x-fix-axp809-ldo_io-registration-error-on-cold-boot.patch regulator-tps65086-fix-25mv-ranges-for-buck-regulators.patch --- diff --git a/queue-4.9/drm-savage-dereferencing-an-error-pointer.patch b/queue-4.9/drm-savage-dereferencing-an-error-pointer.patch new file mode 100644 index 00000000000..7c40621e393 --- /dev/null +++ b/queue-4.9/drm-savage-dereferencing-an-error-pointer.patch @@ -0,0 +1,33 @@ +From f7741aa75e76440f4e9ecfe512feebe9bce33ca8 Mon Sep 17 00:00:00 2001 +From: Dan Carpenter +Date: Wed, 12 Oct 2016 09:22:27 +0300 +Subject: drm/savage: dereferencing an error pointer + +From: Dan Carpenter + +commit f7741aa75e76440f4e9ecfe512feebe9bce33ca8 upstream. + +A recent cleanup changed the kmalloc() + copy_from_user() to +memdup_user() but the error handling wasn't updated so we might call +kfree(-EFAULT) and crash. + +Fixes: a6e3918bcdb1 ('GPU-DRM-Savage: Use memdup_user() rather than duplicating') +Signed-off-by: Dan Carpenter +Signed-off-by: Daniel Vetter +Link: http://patchwork.freedesktop.org/patch/msgid/20161012062227.GU12841@mwanda +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/savage/savage_state.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/gpu/drm/savage/savage_state.c ++++ b/drivers/gpu/drm/savage/savage_state.c +@@ -1004,6 +1004,7 @@ int savage_bci_cmdbuf(struct drm_device + kvb_addr = memdup_user(cmdbuf->vb_addr, cmdbuf->vb_size); + if (IS_ERR(kvb_addr)) { + ret = PTR_ERR(kvb_addr); ++ kvb_addr = NULL; + goto done; + } + cmdbuf->vb_addr = kvb_addr; diff --git a/queue-4.9/drm-tegra-dpaux-fix-error-handling.patch b/queue-4.9/drm-tegra-dpaux-fix-error-handling.patch new file mode 100644 index 00000000000..a734ad88eeb --- /dev/null +++ b/queue-4.9/drm-tegra-dpaux-fix-error-handling.patch @@ -0,0 +1,39 @@ +From 9376cad2073d2c122864754ea5f80025c8507b0b Mon Sep 17 00:00:00 2001 +From: Christophe Jaillet +Date: Fri, 28 Oct 2016 11:09:45 +0200 +Subject: drm/tegra: dpaux: Fix error handling + +From: Christophe Jaillet + +commit 9376cad2073d2c122864754ea5f80025c8507b0b upstream. + +The devm_pinctrl_register() function returns an error pointer or a valid +handle. So checking for NULL here is pointless and can never trigger. + +Check the returned value with IS_ERR instead and propagate this value as +done in the other functions which call devm_pinctrl_register(). + +Fixes: 0751bb5c44fe ("drm/tegra: dpaux: Add pinctrl support") +Signed-off-by: Christophe JAILLET +Acked-by: Jon Hunter +Signed-off-by: Thierry Reding +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/tegra/dpaux.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/tegra/dpaux.c ++++ b/drivers/gpu/drm/tegra/dpaux.c +@@ -539,9 +539,9 @@ static int tegra_dpaux_probe(struct plat + dpaux->desc.owner = THIS_MODULE; + + dpaux->pinctrl = devm_pinctrl_register(&pdev->dev, &dpaux->desc, dpaux); +- if (!dpaux->pinctrl) { ++ if (IS_ERR(dpaux->pinctrl)) { + dev_err(&pdev->dev, "failed to register pincontrol\n"); +- return -ENODEV; ++ return PTR_ERR(dpaux->pinctrl); + } + #endif + /* enable and clear all interrupts */ diff --git a/queue-4.9/drm-vc4-fix-a-couple-error-codes-in-vc4_cl_lookup_bos.patch b/queue-4.9/drm-vc4-fix-a-couple-error-codes-in-vc4_cl_lookup_bos.patch new file mode 100644 index 00000000000..32371081e8e --- /dev/null +++ b/queue-4.9/drm-vc4-fix-a-couple-error-codes-in-vc4_cl_lookup_bos.patch @@ -0,0 +1,44 @@ +From b2cdeb19f16ad984eb5bb9193f793d05a8101511 Mon Sep 17 00:00:00 2001 +From: Dan Carpenter +Date: Thu, 13 Oct 2016 11:54:31 +0300 +Subject: drm/vc4: Fix a couple error codes in vc4_cl_lookup_bos() + +From: Dan Carpenter + +commit b2cdeb19f16ad984eb5bb9193f793d05a8101511 upstream. + +If the allocation fails the current code returns success. If +copy_from_user() fails it returns the number of bytes remaining instead +of -EFAULT. + +Fixes: d5b1a78a772f ("drm/vc4: Add support for drawing 3D frames.") +Signed-off-by: Dan Carpenter +Reviewed-by: Eric Anholt +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/vc4/vc4_gem.c | 9 +++++---- + 1 file changed, 5 insertions(+), 4 deletions(-) + +--- a/drivers/gpu/drm/vc4/vc4_gem.c ++++ b/drivers/gpu/drm/vc4/vc4_gem.c +@@ -544,14 +544,15 @@ vc4_cl_lookup_bos(struct drm_device *dev + + handles = drm_malloc_ab(exec->bo_count, sizeof(uint32_t)); + if (!handles) { ++ ret = -ENOMEM; + DRM_ERROR("Failed to allocate incoming GEM handles\n"); + goto fail; + } + +- ret = copy_from_user(handles, +- (void __user *)(uintptr_t)args->bo_handles, +- exec->bo_count * sizeof(uint32_t)); +- if (ret) { ++ if (copy_from_user(handles, ++ (void __user *)(uintptr_t)args->bo_handles, ++ exec->bo_count * sizeof(uint32_t))) { ++ ret = -EFAULT; + DRM_ERROR("Failed to copy in GEM handles\n"); + goto fail; + } diff --git a/queue-4.9/input-i8042-add-pegatron-touchpad-to-noloop-table.patch b/queue-4.9/input-i8042-add-pegatron-touchpad-to-noloop-table.patch new file mode 100644 index 00000000000..39486cac2f8 --- /dev/null +++ b/queue-4.9/input-i8042-add-pegatron-touchpad-to-noloop-table.patch @@ -0,0 +1,39 @@ +From 41c567a5d7d1a986763e58c3394782813c3bcb03 Mon Sep 17 00:00:00 2001 +From: Marcos Paulo de Souza +Date: Sun, 18 Dec 2016 15:26:12 -0800 +Subject: Input: i8042 - add Pegatron touchpad to noloop table + +From: Marcos Paulo de Souza + +commit 41c567a5d7d1a986763e58c3394782813c3bcb03 upstream. + +Avoid AUX loopback in Pegatron C15B touchpad, so input subsystem is able +to recognize a Synaptics touchpad in the AUX port. + +Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=93791 +(Touchpad is not detected on DNS 0801480 notebook (PEGATRON C15B)) + +Suggested-by: Dmitry Torokhov +Signed-off-by: Marcos Paulo de Souza +Signed-off-by: Dmitry Torokhov +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/input/serio/i8042-x86ia64io.h | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/drivers/input/serio/i8042-x86ia64io.h ++++ b/drivers/input/serio/i8042-x86ia64io.h +@@ -211,6 +211,12 @@ static const struct dmi_system_id __init + DMI_MATCH(DMI_PRODUCT_VERSION, "Rev 1"), + }, + }, ++ { ++ .matches = { ++ DMI_MATCH(DMI_SYS_VENDOR, "PEGATRON CORPORATION"), ++ DMI_MATCH(DMI_PRODUCT_NAME, "C15B"), ++ }, ++ }, + { } + }; + diff --git a/queue-4.9/input-xpad-use-correct-product-id-for-x360w-controllers.patch b/queue-4.9/input-xpad-use-correct-product-id-for-x360w-controllers.patch new file mode 100644 index 00000000000..e7f7e30c564 --- /dev/null +++ b/queue-4.9/input-xpad-use-correct-product-id-for-x360w-controllers.patch @@ -0,0 +1,42 @@ +From b6fc513da50c5dbc457a8ad6b58b046a6a68fd9d Mon Sep 17 00:00:00 2001 +From: Pavel Rojtberg +Date: Tue, 27 Dec 2016 11:44:51 -0800 +Subject: Input: xpad - use correct product id for x360w controllers + +From: Pavel Rojtberg + +commit b6fc513da50c5dbc457a8ad6b58b046a6a68fd9d upstream. + +currently the controllers get the same product id as the wireless +receiver. However the controllers actually have their own product id. + +The patch makes the driver expose the same product id as the windows +driver. + +This improves compatibility when running applications with WINE. + +see https://github.com/paroj/xpad/issues/54 + +Signed-off-by: Pavel Rojtberg +Signed-off-by: Dmitry Torokhov +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/input/joystick/xpad.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/drivers/input/joystick/xpad.c ++++ b/drivers/input/joystick/xpad.c +@@ -1376,6 +1376,12 @@ static int xpad_init_input(struct usb_xp + input_dev->name = xpad->name; + input_dev->phys = xpad->phys; + usb_to_input_id(xpad->udev, &input_dev->id); ++ ++ if (xpad->xtype == XTYPE_XBOX360W) { ++ /* x360w controllers and the receiver have different ids */ ++ input_dev->id.product = 0x02a1; ++ } ++ + input_dev->dev.parent = &xpad->intf->dev; + + input_set_drvdata(input_dev, xpad); diff --git a/queue-4.9/pinctrl-imx-fix-imx_pinctrl_desc-initialization.patch b/queue-4.9/pinctrl-imx-fix-imx_pinctrl_desc-initialization.patch new file mode 100644 index 00000000000..dafd293031c --- /dev/null +++ b/queue-4.9/pinctrl-imx-fix-imx_pinctrl_desc-initialization.patch @@ -0,0 +1,38 @@ +From 8f5983ad6b81070376db9487ce81000c85a16027 Mon Sep 17 00:00:00 2001 +From: Gary Bisson +Date: Thu, 24 Nov 2016 19:11:51 +0100 +Subject: pinctrl: imx: fix imx_pinctrl_desc initialization + +From: Gary Bisson + +commit 8f5983ad6b81070376db9487ce81000c85a16027 upstream. + +Fixes: 6e408ed8be0e ("pinctrl: imx: fix initialization of imx_pinctrl_desc") +Reviewed-by: Vladimir Zapolskiy +Reviewed-by: Peng Fan +Signed-off-by: Gary Bisson +Signed-off-by: Greg Kroah-Hartman + +Signed-off-by: Linus Walleij + +--- + drivers/pinctrl/freescale/pinctrl-imx.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/pinctrl/freescale/pinctrl-imx.c ++++ b/drivers/pinctrl/freescale/pinctrl-imx.c +@@ -778,10 +778,10 @@ int imx_pinctrl_probe(struct platform_de + imx_pinctrl_desc->name = dev_name(&pdev->dev); + imx_pinctrl_desc->pins = info->pins; + imx_pinctrl_desc->npins = info->npins; +- imx_pinctrl_desc->pctlops = &imx_pctrl_ops, +- imx_pinctrl_desc->pmxops = &imx_pmx_ops, +- imx_pinctrl_desc->confops = &imx_pinconf_ops, +- imx_pinctrl_desc->owner = THIS_MODULE, ++ imx_pinctrl_desc->pctlops = &imx_pctrl_ops; ++ imx_pinctrl_desc->pmxops = &imx_pmx_ops; ++ imx_pinctrl_desc->confops = &imx_pinconf_ops; ++ imx_pinctrl_desc->owner = THIS_MODULE; + + ret = imx_pinctrl_probe_dt(pdev, info); + if (ret) { diff --git a/queue-4.9/pinctrl-sh-pfc-r8a7795-use-lookup-function-for-bias-data.patch b/queue-4.9/pinctrl-sh-pfc-r8a7795-use-lookup-function-for-bias-data.patch new file mode 100644 index 00000000000..96f5a4e07e7 --- /dev/null +++ b/queue-4.9/pinctrl-sh-pfc-r8a7795-use-lookup-function-for-bias-data.patch @@ -0,0 +1,425 @@ +From d3b861bccdee2fa9963a2b6c64f74a8d752b9315 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= + +Date: Sat, 12 Nov 2016 17:04:27 +0100 +Subject: pinctrl: sh-pfc: r8a7795: Use lookup function for bias data +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Niklas Söderlund + +commit d3b861bccdee2fa9963a2b6c64f74a8d752b9315 upstream. + +There is a bug in the r8a7795 bias code where a WARN() is trigged +anytime a pin from PUEN0/PUD0 is accessed. + + # cat /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins + + WARNING: CPU: 2 PID: 2391 at drivers/pinctrl/sh-pfc/pfc-r8a7795.c:5364 r8a7795_pinmux_get_bias+0xbc/0xc8 + [..] + Call trace: + [] r8a7795_pinmux_get_bias+0xbc/0xc8 + [] sh_pfc_pinconf_get+0x194/0x270 + [] pin_config_get_for_pin+0x20/0x30 + [] pinconf_generic_dump_one+0x168/0x188 + [] pinconf_generic_dump_pins+0x5c/0x98 + [] pinconf_pins_show+0xc8/0x128 + [] seq_read+0x16c/0x420 + [] full_proxy_read+0x58/0x88 + [] __vfs_read+0x1c/0xf8 + [] vfs_read+0x84/0x148 + [] SyS_read+0x44/0xa0 + [] __sys_trace_return+0x0/0x4 + +This is due to the WARN() check if the reg field of the pullups struct +is zero, and this should be 0 for pins controlled by the PUEN0/PUD0 +registers since PU0 is defined as 0. Change the data structure and use +the generic sh_pfc_pin_to_bias_info() function to get the register +offset and bit information. + +Fixes: 560655247b627ac7 ("pinctrl: sh-pfc: r8a7795: Add bias pinconf support") +Signed-off-by: Niklas Söderlund +Reviewed-by: Laurent Pinchart +Signed-off-by: Geert Uytterhoeven +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 343 +++++++++++++++++------------------ + 1 file changed, 172 insertions(+), 171 deletions(-) + +--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c ++++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +@@ -5188,184 +5188,183 @@ static int r8a7795_pin_to_pocctrl(struct + #define PU5 0x14 + #define PU6 0x18 + +-static const struct { +- u16 reg : 11; +- u16 bit : 5; +-} pullups[] = { +- [RCAR_GP_PIN(2, 11)] = { PU0, 31 }, /* AVB_PHY_INT */ +- [RCAR_GP_PIN(2, 10)] = { PU0, 30 }, /* AVB_MAGIC */ +- [RCAR_GP_PIN(2, 9)] = { PU0, 29 }, /* AVB_MDC */ +- +- [RCAR_GP_PIN(1, 19)] = { PU1, 31 }, /* A19 */ +- [RCAR_GP_PIN(1, 18)] = { PU1, 30 }, /* A18 */ +- [RCAR_GP_PIN(1, 17)] = { PU1, 29 }, /* A17 */ +- [RCAR_GP_PIN(1, 16)] = { PU1, 28 }, /* A16 */ +- [RCAR_GP_PIN(1, 15)] = { PU1, 27 }, /* A15 */ +- [RCAR_GP_PIN(1, 14)] = { PU1, 26 }, /* A14 */ +- [RCAR_GP_PIN(1, 13)] = { PU1, 25 }, /* A13 */ +- [RCAR_GP_PIN(1, 12)] = { PU1, 24 }, /* A12 */ +- [RCAR_GP_PIN(1, 11)] = { PU1, 23 }, /* A11 */ +- [RCAR_GP_PIN(1, 10)] = { PU1, 22 }, /* A10 */ +- [RCAR_GP_PIN(1, 9)] = { PU1, 21 }, /* A9 */ +- [RCAR_GP_PIN(1, 8)] = { PU1, 20 }, /* A8 */ +- [RCAR_GP_PIN(1, 7)] = { PU1, 19 }, /* A7 */ +- [RCAR_GP_PIN(1, 6)] = { PU1, 18 }, /* A6 */ +- [RCAR_GP_PIN(1, 5)] = { PU1, 17 }, /* A5 */ +- [RCAR_GP_PIN(1, 4)] = { PU1, 16 }, /* A4 */ +- [RCAR_GP_PIN(1, 3)] = { PU1, 15 }, /* A3 */ +- [RCAR_GP_PIN(1, 2)] = { PU1, 14 }, /* A2 */ +- [RCAR_GP_PIN(1, 1)] = { PU1, 13 }, /* A1 */ +- [RCAR_GP_PIN(1, 0)] = { PU1, 12 }, /* A0 */ +- [RCAR_GP_PIN(2, 8)] = { PU1, 11 }, /* PWM2_A */ +- [RCAR_GP_PIN(2, 7)] = { PU1, 10 }, /* PWM1_A */ +- [RCAR_GP_PIN(2, 6)] = { PU1, 9 }, /* PWM0 */ +- [RCAR_GP_PIN(2, 5)] = { PU1, 8 }, /* IRQ5 */ +- [RCAR_GP_PIN(2, 4)] = { PU1, 7 }, /* IRQ4 */ +- [RCAR_GP_PIN(2, 3)] = { PU1, 6 }, /* IRQ3 */ +- [RCAR_GP_PIN(2, 2)] = { PU1, 5 }, /* IRQ2 */ +- [RCAR_GP_PIN(2, 1)] = { PU1, 4 }, /* IRQ1 */ +- [RCAR_GP_PIN(2, 0)] = { PU1, 3 }, /* IRQ0 */ +- [RCAR_GP_PIN(2, 14)] = { PU1, 2 }, /* AVB_AVTP_CAPTURE_A */ +- [RCAR_GP_PIN(2, 13)] = { PU1, 1 }, /* AVB_AVTP_MATCH_A */ +- [RCAR_GP_PIN(2, 12)] = { PU1, 0 }, /* AVB_LINK */ +- +- [RCAR_GP_PIN(7, 3)] = { PU2, 29 }, /* HDMI1_CEC */ +- [RCAR_GP_PIN(7, 2)] = { PU2, 28 }, /* HDMI0_CEC */ +- [RCAR_GP_PIN(7, 1)] = { PU2, 27 }, /* AVS2 */ +- [RCAR_GP_PIN(7, 0)] = { PU2, 26 }, /* AVS1 */ +- [RCAR_GP_PIN(0, 15)] = { PU2, 25 }, /* D15 */ +- [RCAR_GP_PIN(0, 14)] = { PU2, 24 }, /* D14 */ +- [RCAR_GP_PIN(0, 13)] = { PU2, 23 }, /* D13 */ +- [RCAR_GP_PIN(0, 12)] = { PU2, 22 }, /* D12 */ +- [RCAR_GP_PIN(0, 11)] = { PU2, 21 }, /* D11 */ +- [RCAR_GP_PIN(0, 10)] = { PU2, 20 }, /* D10 */ +- [RCAR_GP_PIN(0, 9)] = { PU2, 19 }, /* D9 */ +- [RCAR_GP_PIN(0, 8)] = { PU2, 18 }, /* D8 */ +- [RCAR_GP_PIN(0, 7)] = { PU2, 17 }, /* D7 */ +- [RCAR_GP_PIN(0, 6)] = { PU2, 16 }, /* D6 */ +- [RCAR_GP_PIN(0, 5)] = { PU2, 15 }, /* D5 */ +- [RCAR_GP_PIN(0, 4)] = { PU2, 14 }, /* D4 */ +- [RCAR_GP_PIN(0, 3)] = { PU2, 13 }, /* D3 */ +- [RCAR_GP_PIN(0, 2)] = { PU2, 12 }, /* D2 */ +- [RCAR_GP_PIN(0, 1)] = { PU2, 11 }, /* D1 */ +- [RCAR_GP_PIN(0, 0)] = { PU2, 10 }, /* D0 */ +- [RCAR_GP_PIN(1, 27)] = { PU2, 8 }, /* EX_WAIT0_A */ +- [RCAR_GP_PIN(1, 26)] = { PU2, 7 }, /* WE1_N */ +- [RCAR_GP_PIN(1, 25)] = { PU2, 6 }, /* WE0_N */ +- [RCAR_GP_PIN(1, 24)] = { PU2, 5 }, /* RD_WR_N */ +- [RCAR_GP_PIN(1, 23)] = { PU2, 4 }, /* RD_N */ +- [RCAR_GP_PIN(1, 22)] = { PU2, 3 }, /* BS_N */ +- [RCAR_GP_PIN(1, 21)] = { PU2, 2 }, /* CS1_N_A26 */ +- [RCAR_GP_PIN(1, 20)] = { PU2, 1 }, /* CS0_N */ +- +- [RCAR_GP_PIN(4, 9)] = { PU3, 31 }, /* SD3_DAT0 */ +- [RCAR_GP_PIN(4, 8)] = { PU3, 30 }, /* SD3_CMD */ +- [RCAR_GP_PIN(4, 7)] = { PU3, 29 }, /* SD3_CLK */ +- [RCAR_GP_PIN(4, 6)] = { PU3, 28 }, /* SD2_DS */ +- [RCAR_GP_PIN(4, 5)] = { PU3, 27 }, /* SD2_DAT3 */ +- [RCAR_GP_PIN(4, 4)] = { PU3, 26 }, /* SD2_DAT2 */ +- [RCAR_GP_PIN(4, 3)] = { PU3, 25 }, /* SD2_DAT1 */ +- [RCAR_GP_PIN(4, 2)] = { PU3, 24 }, /* SD2_DAT0 */ +- [RCAR_GP_PIN(4, 1)] = { PU3, 23 }, /* SD2_CMD */ +- [RCAR_GP_PIN(4, 0)] = { PU3, 22 }, /* SD2_CLK */ +- [RCAR_GP_PIN(3, 11)] = { PU3, 21 }, /* SD1_DAT3 */ +- [RCAR_GP_PIN(3, 10)] = { PU3, 20 }, /* SD1_DAT2 */ +- [RCAR_GP_PIN(3, 9)] = { PU3, 19 }, /* SD1_DAT1 */ +- [RCAR_GP_PIN(3, 8)] = { PU3, 18 }, /* SD1_DAT0 */ +- [RCAR_GP_PIN(3, 7)] = { PU3, 17 }, /* SD1_CMD */ +- [RCAR_GP_PIN(3, 6)] = { PU3, 16 }, /* SD1_CLK */ +- [RCAR_GP_PIN(3, 5)] = { PU3, 15 }, /* SD0_DAT3 */ +- [RCAR_GP_PIN(3, 4)] = { PU3, 14 }, /* SD0_DAT2 */ +- [RCAR_GP_PIN(3, 3)] = { PU3, 13 }, /* SD0_DAT1 */ +- [RCAR_GP_PIN(3, 2)] = { PU3, 12 }, /* SD0_DAT0 */ +- [RCAR_GP_PIN(3, 1)] = { PU3, 11 }, /* SD0_CMD */ +- [RCAR_GP_PIN(3, 0)] = { PU3, 10 }, /* SD0_CLK */ +- +- [RCAR_GP_PIN(5, 19)] = { PU4, 31 }, /* MSIOF0_SS1 */ +- [RCAR_GP_PIN(5, 18)] = { PU4, 30 }, /* MSIOF0_SYNC */ +- [RCAR_GP_PIN(5, 17)] = { PU4, 29 }, /* MSIOF0_SCK */ +- [RCAR_GP_PIN(5, 16)] = { PU4, 28 }, /* HRTS0_N */ +- [RCAR_GP_PIN(5, 15)] = { PU4, 27 }, /* HCTS0_N */ +- [RCAR_GP_PIN(5, 14)] = { PU4, 26 }, /* HTX0 */ +- [RCAR_GP_PIN(5, 13)] = { PU4, 25 }, /* HRX0 */ +- [RCAR_GP_PIN(5, 12)] = { PU4, 24 }, /* HSCK0 */ +- [RCAR_GP_PIN(5, 11)] = { PU4, 23 }, /* RX2_A */ +- [RCAR_GP_PIN(5, 10)] = { PU4, 22 }, /* TX2_A */ +- [RCAR_GP_PIN(5, 9)] = { PU4, 21 }, /* SCK2 */ +- [RCAR_GP_PIN(5, 8)] = { PU4, 20 }, /* RTS1_N_TANS */ +- [RCAR_GP_PIN(5, 7)] = { PU4, 19 }, /* CTS1_N */ +- [RCAR_GP_PIN(5, 6)] = { PU4, 18 }, /* TX1_A */ +- [RCAR_GP_PIN(5, 5)] = { PU4, 17 }, /* RX1_A */ +- [RCAR_GP_PIN(5, 4)] = { PU4, 16 }, /* RTS0_N_TANS */ +- [RCAR_GP_PIN(5, 3)] = { PU4, 15 }, /* CTS0_N */ +- [RCAR_GP_PIN(5, 2)] = { PU4, 14 }, /* TX0 */ +- [RCAR_GP_PIN(5, 1)] = { PU4, 13 }, /* RX0 */ +- [RCAR_GP_PIN(5, 0)] = { PU4, 12 }, /* SCK0 */ +- [RCAR_GP_PIN(3, 15)] = { PU4, 11 }, /* SD1_WP */ +- [RCAR_GP_PIN(3, 14)] = { PU4, 10 }, /* SD1_CD */ +- [RCAR_GP_PIN(3, 13)] = { PU4, 9 }, /* SD0_WP */ +- [RCAR_GP_PIN(3, 12)] = { PU4, 8 }, /* SD0_CD */ +- [RCAR_GP_PIN(4, 17)] = { PU4, 7 }, /* SD3_DS */ +- [RCAR_GP_PIN(4, 16)] = { PU4, 6 }, /* SD3_DAT7 */ +- [RCAR_GP_PIN(4, 15)] = { PU4, 5 }, /* SD3_DAT6 */ +- [RCAR_GP_PIN(4, 14)] = { PU4, 4 }, /* SD3_DAT5 */ +- [RCAR_GP_PIN(4, 13)] = { PU4, 3 }, /* SD3_DAT4 */ +- [RCAR_GP_PIN(4, 12)] = { PU4, 2 }, /* SD3_DAT3 */ +- [RCAR_GP_PIN(4, 11)] = { PU4, 1 }, /* SD3_DAT2 */ +- [RCAR_GP_PIN(4, 10)] = { PU4, 0 }, /* SD3_DAT1 */ +- +- [RCAR_GP_PIN(6, 24)] = { PU5, 31 }, /* USB0_PWEN */ +- [RCAR_GP_PIN(6, 23)] = { PU5, 30 }, /* AUDIO_CLKB_B */ +- [RCAR_GP_PIN(6, 22)] = { PU5, 29 }, /* AUDIO_CLKA_A */ +- [RCAR_GP_PIN(6, 21)] = { PU5, 28 }, /* SSI_SDATA9_A */ +- [RCAR_GP_PIN(6, 20)] = { PU5, 27 }, /* SSI_SDATA8 */ +- [RCAR_GP_PIN(6, 19)] = { PU5, 26 }, /* SSI_SDATA7 */ +- [RCAR_GP_PIN(6, 18)] = { PU5, 25 }, /* SSI_WS78 */ +- [RCAR_GP_PIN(6, 17)] = { PU5, 24 }, /* SSI_SCK78 */ +- [RCAR_GP_PIN(6, 16)] = { PU5, 23 }, /* SSI_SDATA6 */ +- [RCAR_GP_PIN(6, 15)] = { PU5, 22 }, /* SSI_WS6 */ +- [RCAR_GP_PIN(6, 14)] = { PU5, 21 }, /* SSI_SCK6 */ +- [RCAR_GP_PIN(6, 13)] = { PU5, 20 }, /* SSI_SDATA5 */ +- [RCAR_GP_PIN(6, 12)] = { PU5, 19 }, /* SSI_WS5 */ +- [RCAR_GP_PIN(6, 11)] = { PU5, 18 }, /* SSI_SCK5 */ +- [RCAR_GP_PIN(6, 10)] = { PU5, 17 }, /* SSI_SDATA4 */ +- [RCAR_GP_PIN(6, 9)] = { PU5, 16 }, /* SSI_WS4 */ +- [RCAR_GP_PIN(6, 8)] = { PU5, 15 }, /* SSI_SCK4 */ +- [RCAR_GP_PIN(6, 7)] = { PU5, 14 }, /* SSI_SDATA3 */ +- [RCAR_GP_PIN(6, 6)] = { PU5, 13 }, /* SSI_WS34 */ +- [RCAR_GP_PIN(6, 5)] = { PU5, 12 }, /* SSI_SCK34 */ +- [RCAR_GP_PIN(6, 4)] = { PU5, 11 }, /* SSI_SDATA2_A */ +- [RCAR_GP_PIN(6, 3)] = { PU5, 10 }, /* SSI_SDATA1_A */ +- [RCAR_GP_PIN(6, 2)] = { PU5, 9 }, /* SSI_SDATA0 */ +- [RCAR_GP_PIN(6, 1)] = { PU5, 8 }, /* SSI_WS01239 */ +- [RCAR_GP_PIN(6, 0)] = { PU5, 7 }, /* SSI_SCK01239 */ +- [RCAR_GP_PIN(5, 25)] = { PU5, 5 }, /* MLB_DAT */ +- [RCAR_GP_PIN(5, 24)] = { PU5, 4 }, /* MLB_SIG */ +- [RCAR_GP_PIN(5, 23)] = { PU5, 3 }, /* MLB_CLK */ +- [RCAR_GP_PIN(5, 22)] = { PU5, 2 }, /* MSIOF0_RXD */ +- [RCAR_GP_PIN(5, 21)] = { PU5, 1 }, /* MSIOF0_SS2 */ +- [RCAR_GP_PIN(5, 20)] = { PU5, 0 }, /* MSIOF0_TXD */ +- +- [RCAR_GP_PIN(6, 31)] = { PU6, 6 }, /* USB31_OVC */ +- [RCAR_GP_PIN(6, 30)] = { PU6, 5 }, /* USB31_PWEN */ +- [RCAR_GP_PIN(6, 29)] = { PU6, 4 }, /* USB30_OVC */ +- [RCAR_GP_PIN(6, 28)] = { PU6, 3 }, /* USB30_PWEN */ +- [RCAR_GP_PIN(6, 27)] = { PU6, 2 }, /* USB1_OVC */ +- [RCAR_GP_PIN(6, 26)] = { PU6, 1 }, /* USB1_PWEN */ +- [RCAR_GP_PIN(6, 25)] = { PU6, 0 }, /* USB0_OVC */ ++static const struct sh_pfc_bias_info bias_info[] = { ++ { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */ ++ { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */ ++ { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */ ++ ++ { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */ ++ { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */ ++ { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */ ++ { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */ ++ { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */ ++ { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */ ++ { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */ ++ { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */ ++ { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */ ++ { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */ ++ { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */ ++ { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */ ++ { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */ ++ { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */ ++ { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */ ++ { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */ ++ { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */ ++ { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */ ++ { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */ ++ { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */ ++ { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */ ++ { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */ ++ { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */ ++ { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */ ++ { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */ ++ { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */ ++ { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */ ++ { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */ ++ { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */ ++ { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */ ++ { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */ ++ { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */ ++ ++ { RCAR_GP_PIN(7, 3), PU2, 29 }, /* HDMI1_CEC */ ++ { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */ ++ { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */ ++ { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */ ++ { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */ ++ { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */ ++ { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */ ++ { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */ ++ { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */ ++ { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */ ++ { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */ ++ { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */ ++ { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */ ++ { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */ ++ { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */ ++ { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */ ++ { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */ ++ { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */ ++ { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */ ++ { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */ ++ { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */ ++ { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */ ++ { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */ ++ { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */ ++ { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */ ++ { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */ ++ { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N_A26 */ ++ { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */ ++ ++ { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */ ++ { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */ ++ { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */ ++ { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */ ++ { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */ ++ { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */ ++ { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */ ++ { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */ ++ { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */ ++ { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */ ++ { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */ ++ { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */ ++ { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */ ++ { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */ ++ { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */ ++ { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */ ++ { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */ ++ { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */ ++ { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */ ++ { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */ ++ { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */ ++ { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */ ++ ++ { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */ ++ { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */ ++ { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */ ++ { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */ ++ { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */ ++ { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */ ++ { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */ ++ { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */ ++ { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */ ++ { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */ ++ { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */ ++ { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */ ++ { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */ ++ { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */ ++ { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */ ++ { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */ ++ { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */ ++ { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */ ++ { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */ ++ { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */ ++ { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */ ++ { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */ ++ { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */ ++ { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */ ++ { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */ ++ { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */ ++ { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */ ++ { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */ ++ { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */ ++ { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */ ++ { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */ ++ { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */ ++ ++ { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */ ++ { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */ ++ { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */ ++ { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */ ++ { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */ ++ { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */ ++ { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */ ++ { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */ ++ { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */ ++ { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */ ++ { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */ ++ { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */ ++ { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */ ++ { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */ ++ { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */ ++ { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */ ++ { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */ ++ { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */ ++ { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS34 */ ++ { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK34 */ ++ { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */ ++ { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */ ++ { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */ ++ { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */ ++ { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */ ++ { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */ ++ { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */ ++ { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */ ++ { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */ ++ { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */ ++ { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */ ++ ++ { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB31_OVC */ ++ { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB31_PWEN */ ++ { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */ ++ { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */ ++ { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */ ++ { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */ ++ { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */ + }; + + static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc, + unsigned int pin) + { ++ const struct sh_pfc_bias_info *info; + u32 reg; + u32 bit; + +- if (WARN_ON_ONCE(!pullups[pin].reg)) ++ info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin); ++ if (!info) + return PIN_CONFIG_BIAS_DISABLE; + +- reg = pullups[pin].reg; +- bit = BIT(pullups[pin].bit); ++ reg = info->reg; ++ bit = BIT(info->bit); + + if (sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit) { + if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit) +@@ -5379,15 +5378,17 @@ static unsigned int r8a7795_pinmux_get_b + static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, + unsigned int bias) + { ++ const struct sh_pfc_bias_info *info; + u32 enable, updown; + u32 reg; + u32 bit; + +- if (WARN_ON_ONCE(!pullups[pin].reg)) ++ info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin); ++ if (!info) + return; + +- reg = pullups[pin].reg; +- bit = BIT(pullups[pin].bit); ++ reg = info->reg; ++ bit = BIT(info->bit); + + enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit; + if (bias != PIN_CONFIG_BIAS_DISABLE) diff --git a/queue-4.9/regulator-axp20x-fix-axp809-ldo_io-registration-error-on-cold-boot.patch b/queue-4.9/regulator-axp20x-fix-axp809-ldo_io-registration-error-on-cold-boot.patch new file mode 100644 index 00000000000..7e643a18169 --- /dev/null +++ b/queue-4.9/regulator-axp20x-fix-axp809-ldo_io-registration-error-on-cold-boot.patch @@ -0,0 +1,66 @@ +From 618c808968852609d2d9f0e5cfc351a4807ef8d0 Mon Sep 17 00:00:00 2001 +From: Chen-Yu Tsai +Date: Fri, 11 Nov 2016 11:12:43 +0800 +Subject: regulator: axp20x: Fix axp809 ldo_io registration error on cold boot + +From: Chen-Yu Tsai + +commit 618c808968852609d2d9f0e5cfc351a4807ef8d0 upstream. + +The maximum supported voltage for ldo_io# is 3.3V, but on cold boot +the selector comes up at 0x1f, which maps to 3.8V. This was previously +corrected by Allwinner's U-boot, which set all regulators on the PMICs +to some pre-configured voltage. With recent progress in U-boot SPL +support, this is no longer the case. In any case we should handle +this quirk in the kernel driver as well. + +This invalid setting causes _regulator_get_voltage() to fail with -EINVAL +which causes regulator registration to fail when constrains are used: + +[ 1.054181] vcc-pg: failed to get the current voltage(-22) +[ 1.059670] axp20x-regulator axp20x-regulator.0: Failed to register ldo_io0 +[ 1.069749] axp20x-regulator: probe of axp20x-regulator.0 failed with error -22 + +This commits makes the axp20x regulator driver accept the 0x1f register +value, fixing this. + +The datasheet does not guarantee reliable operation above 3.3V, so on +boards where this regulator is used the regulator-max-microvolt setting +must be 3.3V or less. + +This is essentially the same as the commit f40d4896bf32 ("regulator: +axp20x: Fix axp22x ldo_io registration error on cold boot") for AXP22x +PMICs. + +Fixes: a51f9f4622a3 ("regulator: axp20x: support AXP809 variant") +Signed-off-by: Chen-Yu Tsai +Signed-off-by: Mark Brown +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/regulator/axp20x-regulator.c | 12 ++++++++++-- + 1 file changed, 10 insertions(+), 2 deletions(-) + +--- a/drivers/regulator/axp20x-regulator.c ++++ b/drivers/regulator/axp20x-regulator.c +@@ -337,10 +337,18 @@ static const struct regulator_desc axp80 + AXP22X_ELDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(1)), + AXP_DESC(AXP809, ELDO3, "eldo3", "eldoin", 700, 3300, 100, + AXP22X_ELDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(2)), +- AXP_DESC_IO(AXP809, LDO_IO0, "ldo_io0", "ips", 700, 3300, 100, ++ /* ++ * Note the datasheet only guarantees reliable operation up to ++ * 3.3V, this needs to be enforced via dts provided constraints ++ */ ++ AXP_DESC_IO(AXP809, LDO_IO0, "ldo_io0", "ips", 700, 3800, 100, + AXP22X_LDO_IO0_V_OUT, 0x1f, AXP20X_GPIO0_CTRL, 0x07, + AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), +- AXP_DESC_IO(AXP809, LDO_IO1, "ldo_io1", "ips", 700, 3300, 100, ++ /* ++ * Note the datasheet only guarantees reliable operation up to ++ * 3.3V, this needs to be enforced via dts provided constraints ++ */ ++ AXP_DESC_IO(AXP809, LDO_IO1, "ldo_io1", "ips", 700, 3800, 100, + AXP22X_LDO_IO1_V_OUT, 0x1f, AXP20X_GPIO1_CTRL, 0x07, + AXP22X_IO_ENABLED, AXP22X_IO_DISABLED), + AXP_DESC_FIXED(AXP809, RTC_LDO, "rtc_ldo", "ips", 1800), diff --git a/queue-4.9/regulator-tps65086-fix-25mv-ranges-for-buck-regulators.patch b/queue-4.9/regulator-tps65086-fix-25mv-ranges-for-buck-regulators.patch new file mode 100644 index 00000000000..68341e0233b --- /dev/null +++ b/queue-4.9/regulator-tps65086-fix-25mv-ranges-for-buck-regulators.patch @@ -0,0 +1,143 @@ +From d8ca5bd158f738c4fa6974ee388c381f64db7905 Mon Sep 17 00:00:00 2001 +From: "Andrew F. Davis" +Date: Thu, 1 Dec 2016 10:44:16 -0600 +Subject: regulator: tps65086: Fix 25mV ranges for BUCK regulators + +From: Andrew F. Davis + +commit d8ca5bd158f738c4fa6974ee388c381f64db7905 upstream. + +The BUCK regulators 3, 4, and 5 also have a 10mV step mode, +adjust the tables and logic to reflect the data-sheet for +these regulators. + +fixes: d2a2e729a666 ("regulator: tps65086: Add regulator driver for the TPS65086 PMIC") +Signed-off-by: Andrew F. Davis +Signed-off-by: Mark Brown +Signed-off-by: Greg Kroah-Hartman + +--- + Documentation/devicetree/bindings/mfd/tps65086.txt | 2 + drivers/regulator/tps65086-regulator.c | 54 ++++++++++----------- + 2 files changed, 29 insertions(+), 27 deletions(-) + +--- a/Documentation/devicetree/bindings/mfd/tps65086.txt ++++ b/Documentation/devicetree/bindings/mfd/tps65086.txt +@@ -23,7 +23,7 @@ Required properties: + defined below. + + Optional regulator properties: +- - ti,regulator-step-size-25mv : This is applicable for buck[1,2,6], set this ++ - ti,regulator-step-size-25mv : This is applicable for buck[1-6], set this + if the regulator is factory set with a 25mv + step voltage mapping. + - ti,regulator-decay : This is applicable for buck[1-6], set this if +--- a/drivers/regulator/tps65086-regulator.c ++++ b/drivers/regulator/tps65086-regulator.c +@@ -71,18 +71,17 @@ struct tps65086_regulator { + unsigned int decay_mask; + }; + +-static const struct regulator_linear_range tps65086_buck126_10mv_ranges[] = { ++static const struct regulator_linear_range tps65086_10mv_ranges[] = { + REGULATOR_LINEAR_RANGE(0, 0x0, 0x0, 0), + REGULATOR_LINEAR_RANGE(410000, 0x1, 0x7F, 10000), + }; + + static const struct regulator_linear_range tps65086_buck126_25mv_ranges[] = { +- REGULATOR_LINEAR_RANGE(0, 0x0, 0x0, 0), +- REGULATOR_LINEAR_RANGE(1000000, 0x1, 0x18, 0), ++ REGULATOR_LINEAR_RANGE(1000000, 0x0, 0x18, 0), + REGULATOR_LINEAR_RANGE(1025000, 0x19, 0x7F, 25000), + }; + +-static const struct regulator_linear_range tps65086_buck345_ranges[] = { ++static const struct regulator_linear_range tps65086_buck345_25mv_ranges[] = { + REGULATOR_LINEAR_RANGE(0, 0x0, 0x0, 0), + REGULATOR_LINEAR_RANGE(425000, 0x1, 0x7F, 25000), + }; +@@ -125,27 +124,27 @@ static int tps65086_of_parse_cb(struct d + static struct tps65086_regulator regulators[] = { + TPS65086_REGULATOR("BUCK1", "buck1", BUCK1, 0x80, TPS65086_BUCK1CTRL, + BUCK_VID_MASK, TPS65086_BUCK123CTRL, BIT(0), +- tps65086_buck126_10mv_ranges, TPS65086_BUCK1CTRL, ++ tps65086_10mv_ranges, TPS65086_BUCK1CTRL, + BIT(0)), + TPS65086_REGULATOR("BUCK2", "buck2", BUCK2, 0x80, TPS65086_BUCK2CTRL, + BUCK_VID_MASK, TPS65086_BUCK123CTRL, BIT(1), +- tps65086_buck126_10mv_ranges, TPS65086_BUCK2CTRL, ++ tps65086_10mv_ranges, TPS65086_BUCK2CTRL, + BIT(0)), + TPS65086_REGULATOR("BUCK3", "buck3", BUCK3, 0x80, TPS65086_BUCK3VID, + BUCK_VID_MASK, TPS65086_BUCK123CTRL, BIT(2), +- tps65086_buck345_ranges, TPS65086_BUCK3DECAY, ++ tps65086_10mv_ranges, TPS65086_BUCK3DECAY, + BIT(0)), + TPS65086_REGULATOR("BUCK4", "buck4", BUCK4, 0x80, TPS65086_BUCK4VID, + BUCK_VID_MASK, TPS65086_BUCK4CTRL, BIT(0), +- tps65086_buck345_ranges, TPS65086_BUCK4VID, ++ tps65086_10mv_ranges, TPS65086_BUCK4VID, + BIT(0)), + TPS65086_REGULATOR("BUCK5", "buck5", BUCK5, 0x80, TPS65086_BUCK5VID, + BUCK_VID_MASK, TPS65086_BUCK5CTRL, BIT(0), +- tps65086_buck345_ranges, TPS65086_BUCK5CTRL, ++ tps65086_10mv_ranges, TPS65086_BUCK5CTRL, + BIT(0)), + TPS65086_REGULATOR("BUCK6", "buck6", BUCK6, 0x80, TPS65086_BUCK6VID, + BUCK_VID_MASK, TPS65086_BUCK6CTRL, BIT(0), +- tps65086_buck126_10mv_ranges, TPS65086_BUCK6CTRL, ++ tps65086_10mv_ranges, TPS65086_BUCK6CTRL, + BIT(0)), + TPS65086_REGULATOR("LDOA1", "ldoa1", LDOA1, 0xF, TPS65086_LDOA1CTRL, + VDOA1_VID_MASK, TPS65086_LDOA1CTRL, BIT(0), +@@ -162,18 +161,6 @@ static struct tps65086_regulator regulat + TPS65086_SWITCH("VTT", "vtt", VTT, TPS65086_SWVTT_EN, BIT(4)), + }; + +-static inline bool has_25mv_mode(int id) +-{ +- switch (id) { +- case BUCK1: +- case BUCK2: +- case BUCK6: +- return true; +- default: +- return false; +- } +-} +- + static int tps65086_of_parse_cb(struct device_node *dev, + const struct regulator_desc *desc, + struct regulator_config *config) +@@ -181,12 +168,27 @@ static int tps65086_of_parse_cb(struct d + int ret; + + /* Check for 25mV step mode */ +- if (has_25mv_mode(desc->id) && +- of_property_read_bool(config->of_node, "ti,regulator-step-size-25mv")) { +- regulators[desc->id].desc.linear_ranges = ++ if (of_property_read_bool(config->of_node, "ti,regulator-step-size-25mv")) { ++ switch (desc->id) { ++ case BUCK1: ++ case BUCK2: ++ case BUCK6: ++ regulators[desc->id].desc.linear_ranges = + tps65086_buck126_25mv_ranges; +- regulators[desc->id].desc.n_linear_ranges = ++ regulators[desc->id].desc.n_linear_ranges = + ARRAY_SIZE(tps65086_buck126_25mv_ranges); ++ break; ++ case BUCK3: ++ case BUCK4: ++ case BUCK5: ++ regulators[desc->id].desc.linear_ranges = ++ tps65086_buck345_25mv_ranges; ++ regulators[desc->id].desc.n_linear_ranges = ++ ARRAY_SIZE(tps65086_buck345_25mv_ranges); ++ break; ++ default: ++ dev_warn(config->dev, "25mV step mode only valid for BUCK regulators\n"); ++ } + } + + /* Check for decay mode */