From: Greg Kroah-Hartman Date: Wed, 23 Sep 2015 05:13:18 +0000 (-0700) Subject: 4.2-stable patches X-Git-Tag: v4.1.9~40 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=491c22514cfdc5942f857e9ca7c5d0194e211418;p=thirdparty%2Fkernel%2Fstable-queue.git 4.2-stable patches added patches: drm-i915-don-t-use-link_bw-for-pll-setup.patch i915-set-ddi_pll_sel-in-dp-mst-path.patch --- diff --git a/queue-4.2/drm-i915-don-t-use-link_bw-for-pll-setup.patch b/queue-4.2/drm-i915-don-t-use-link_bw-for-pll-setup.patch new file mode 100644 index 00000000000..c3b79413bdb --- /dev/null +++ b/queue-4.2/drm-i915-don-t-use-link_bw-for-pll-setup.patch @@ -0,0 +1,186 @@ +From 7e6313a2516dbcd168f4ae36f0abe1a9227106b5 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= +Date: Tue, 11 Aug 2015 20:21:46 +0300 +Subject: drm/i915: Don't use link_bw for PLL setup +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= + +commit 7e6313a2516dbcd168f4ae36f0abe1a9227106b5 upstream. + +Use port_clock instead of link_bw when picking the PLL parameters for +DP. link_bw may be zero with an eDP 1.4 sink that supports +DP_LINK_RATE_SET so we shouldn't use it for anything other than feed it +to the sink appropriately. + +v2: Fix typo in commit message (Sivakumar) + +Reviewed-by: Sivakumar Thulasimani +Signed-off-by: Ville Syrjälä +Signed-off-by: Daniel Vetter +[Jani: cherry-picked from future.] +Signed-off-by: Jani Nikula +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/intel_ddi.c | 11 +++------ + drivers/gpu/drm/i915/intel_dp.c | 44 +++++++++++++++++++-------------------- + 2 files changed, 26 insertions(+), 29 deletions(-) + +--- a/drivers/gpu/drm/i915/intel_ddi.c ++++ b/drivers/gpu/drm/i915/intel_ddi.c +@@ -1293,17 +1293,14 @@ skl_ddi_pll_select(struct intel_crtc *in + DPLL_CFGCR2_PDIV(wrpll_params.pdiv) | + wrpll_params.central_freq; + } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) { +- struct drm_encoder *encoder = &intel_encoder->base; +- struct intel_dp *intel_dp = enc_to_intel_dp(encoder); +- +- switch (intel_dp->link_bw) { +- case DP_LINK_BW_1_62: ++ switch (crtc_state->port_clock / 2) { ++ case 81000: + ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0); + break; +- case DP_LINK_BW_2_7: ++ case 135000: + ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0); + break; +- case DP_LINK_BW_5_4: ++ case 270000: + ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0); + break; + } +--- a/drivers/gpu/drm/i915/intel_dp.c ++++ b/drivers/gpu/drm/i915/intel_dp.c +@@ -48,28 +48,28 @@ + #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) + + struct dp_link_dpll { +- int link_bw; ++ int clock; + struct dpll dpll; + }; + + static const struct dp_link_dpll gen4_dpll[] = { +- { DP_LINK_BW_1_62, ++ { 162000, + { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, +- { DP_LINK_BW_2_7, ++ { 270000, + { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } + }; + + static const struct dp_link_dpll pch_dpll[] = { +- { DP_LINK_BW_1_62, ++ { 162000, + { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, +- { DP_LINK_BW_2_7, ++ { 270000, + { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } + }; + + static const struct dp_link_dpll vlv_dpll[] = { +- { DP_LINK_BW_1_62, ++ { 162000, + { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, +- { DP_LINK_BW_2_7, ++ { 270000, + { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } + }; + +@@ -83,11 +83,11 @@ static const struct dp_link_dpll chv_dpl + * m2 is stored in fixed point format using formula below + * (m2_int << 22) | m2_fraction + */ +- { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */ ++ { 162000, /* m2_int = 32, m2_fraction = 1677722 */ + { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, +- { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */ ++ { 270000, /* m2_int = 27, m2_fraction = 0 */ + { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, +- { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */ ++ { 540000, /* m2_int = 27, m2_fraction = 0 */ + { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } + }; + +@@ -1089,7 +1089,7 @@ intel_dp_connector_unregister(struct int + } + + static void +-skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock) ++skl_edp_set_pll_config(struct intel_crtc_state *pipe_config) + { + u32 ctrl1; + +@@ -1101,7 +1101,7 @@ skl_edp_set_pll_config(struct intel_crtc + pipe_config->dpll_hw_state.cfgcr2 = 0; + + ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0); +- switch (link_clock / 2) { ++ switch (pipe_config->port_clock / 2) { + case 81000: + ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, + SKL_DPLL0); +@@ -1135,19 +1135,19 @@ skl_edp_set_pll_config(struct intel_crtc + } + + static void +-hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw) ++hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config) + { + memset(&pipe_config->dpll_hw_state, 0, + sizeof(pipe_config->dpll_hw_state)); + +- switch (link_bw) { +- case DP_LINK_BW_1_62: ++ switch (pipe_config->port_clock / 2) { ++ case 81000: + pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; + break; +- case DP_LINK_BW_2_7: ++ case 135000: + pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; + break; +- case DP_LINK_BW_5_4: ++ case 270000: + pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; + break; + } +@@ -1198,7 +1198,7 @@ intel_dp_source_rates(struct drm_device + + static void + intel_dp_set_clock(struct intel_encoder *encoder, +- struct intel_crtc_state *pipe_config, int link_bw) ++ struct intel_crtc_state *pipe_config) + { + struct drm_device *dev = encoder->base.dev; + const struct dp_link_dpll *divisor = NULL; +@@ -1220,7 +1220,7 @@ intel_dp_set_clock(struct intel_encoder + + if (divisor && count) { + for (i = 0; i < count; i++) { +- if (link_bw == divisor[i].link_bw) { ++ if (pipe_config->port_clock == divisor[i].clock) { + pipe_config->dpll = divisor[i].dpll; + pipe_config->clock_set = true; + break; +@@ -1494,13 +1494,13 @@ found: + } + + if (IS_SKYLAKE(dev) && is_edp(intel_dp)) +- skl_edp_set_pll_config(pipe_config, common_rates[clock]); ++ skl_edp_set_pll_config(pipe_config); + else if (IS_BROXTON(dev)) + /* handled in ddi */; + else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) +- hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw); ++ hsw_dp_set_ddi_pll_sel(pipe_config); + else +- intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw); ++ intel_dp_set_clock(encoder, pipe_config); + + return true; + } diff --git a/queue-4.2/i915-set-ddi_pll_sel-in-dp-mst-path.patch b/queue-4.2/i915-set-ddi_pll_sel-in-dp-mst-path.patch new file mode 100644 index 00000000000..d5fd42b95a0 --- /dev/null +++ b/queue-4.2/i915-set-ddi_pll_sel-in-dp-mst-path.patch @@ -0,0 +1,82 @@ +From 6fa2d197936ba0b8936e813d0adecefac160062b Mon Sep 17 00:00:00 2001 +From: Ander Conselvan de Oliveira +Date: Mon, 31 Aug 2015 11:23:28 +0300 +Subject: i915: Set ddi_pll_sel in DP MST path +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ander Conselvan de Oliveira + +commit 6fa2d197936ba0b8936e813d0adecefac160062b upstream. + +The DP MST encoder config function never sets ddi_pll_sel, even though +its value is programmed in its ->pre_enable() hook. That used to work +because a new pipe_config was kzalloc'ed at every modeset, and the value +of zero selects the highest clock for the PLL. Starting with the commit +below, the value of ddi_pll_sel is preserved through modesets, and since +the correct value wasn't properly setup by the MST code, it could lead +to warnings and blank screens. + +commit 8504c74c7ae48b4b8ed1f1c0acf67482a7f45c93 +Author: Ander Conselvan de Oliveira +Date: Fri May 15 11:51:50 2015 +0300 + + drm/i915: Preserve ddi_pll_sel when allocating new pipe_config + +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91628 +Cc: Timo Aaltonen +Cc: Luciano Coelho +Signed-off-by: Ander Conselvan de Oliveira +Reviewed-by: Ville Syrjälä +Signed-off-by: Jani Nikula +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/intel_dp.c | 2 +- + drivers/gpu/drm/i915/intel_dp_mst.c | 5 +++++ + drivers/gpu/drm/i915/intel_drv.h | 1 + + 3 files changed, 7 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/i915/intel_dp.c ++++ b/drivers/gpu/drm/i915/intel_dp.c +@@ -1134,7 +1134,7 @@ skl_edp_set_pll_config(struct intel_crtc + pipe_config->dpll_hw_state.ctrl1 = ctrl1; + } + +-static void ++void + hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config) + { + memset(&pipe_config->dpll_hw_state, 0, +--- a/drivers/gpu/drm/i915/intel_dp_mst.c ++++ b/drivers/gpu/drm/i915/intel_dp_mst.c +@@ -33,6 +33,7 @@ + static bool intel_dp_mst_compute_config(struct intel_encoder *encoder, + struct intel_crtc_state *pipe_config) + { ++ struct drm_device *dev = encoder->base.dev; + struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); + struct intel_digital_port *intel_dig_port = intel_mst->primary; + struct intel_dp *intel_dp = &intel_dig_port->dp; +@@ -97,6 +98,10 @@ static bool intel_dp_mst_compute_config( + &pipe_config->dp_m_n); + + pipe_config->dp_m_n.tu = slots; ++ ++ if (IS_HASWELL(dev) || IS_BROADWELL(dev)) ++ hsw_dp_set_ddi_pll_sel(pipe_config); ++ + return true; + + } +--- a/drivers/gpu/drm/i915/intel_drv.h ++++ b/drivers/gpu/drm/i915/intel_drv.h +@@ -1194,6 +1194,7 @@ void intel_edp_drrs_disable(struct intel + void intel_edp_drrs_invalidate(struct drm_device *dev, + unsigned frontbuffer_bits); + void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits); ++void hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config); + + /* intel_dp_mst.c */ + int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id); diff --git a/queue-4.2/series b/queue-4.2/series index 47b5892e3aa..4a430b8dd8e 100644 --- a/queue-4.2/series +++ b/queue-4.2/series @@ -61,3 +61,5 @@ cifs-fix-type-confusion-in-copy-offload-ioctl.patch add-radeon-suspend-resume-quirk-for-hp-compaq-dc5750.patch mm-check-if-section-present-during-memory-block-registering.patch x86-mm-initialize-pmd_idx-in-page_table_range_init_count.patch +drm-i915-don-t-use-link_bw-for-pll-setup.patch +i915-set-ddi_pll_sel-in-dp-mst-path.patch