From: Greg Kroah-Hartman Date: Fri, 6 Dec 2024 13:22:01 +0000 (+0100) Subject: 6.12-stable patches X-Git-Tag: v6.6.64~9 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=491ee105dfb706734f83ce1f38bee1b1d1e206c8;p=thirdparty%2Fkernel%2Fstable-queue.git 6.12-stable patches added patches: drm-amd-add-some-missing-straps-from-nbio-7.11.0.patch drm-amd-display-fix-handling-of-plane-refcount.patch drm-amd-display-remove-pipe_dto_src_sel-programming-from-set_dtbclk_dto.patch drm-amd-display-update-pipe-selection-policy-to-check-head-pipe.patch drm-amd-fix-initialization-mistake-for-nbio-7.11-devices.patch drm-amd-pm-disable-pcie-speed-switching-on-intel-platform-for-smu-v14.0.2-3.patch drm-amd-pm-remove-arcturus-min-power-limit.patch drm-amd-pm-skip-setting-the-power-source-on-smu-v14.0.2-3.patch drm-amd-pm-update-current_socclk-and-current_uclk-in-gpu_metrics-on-smu-v13.0.7.patch drm-amdgpu-fix-usage-slab-after-free.patch drm-amdgpu-pm-add-gen5-display-to-the-user-on-smu-v14.0.2-3.patch drm-amdkfd-use-the-correct-wptr-size.patch drm-bridge-it6505-fix-inverted-reset-polarity.patch drm-etnaviv-flush-shader-l1-cache-after-user-commandstream.patch drm-fbdev-dma-select-fb_deferred_io.patch drm-mediatek-fix-child-node-refcount-handling-in-early-exit.patch drm-panel-jd9365da-h3-remove-unused-num_init_cmds-structure-member.patch drm-panic-fix-uninitialized-spinlock-acquisition-with-config_drm_panic-n.patch drm-sti-avoid-potential-dereference-of-error-pointers-in-sti_gdp_atomic_check.patch drm-sti-avoid-potential-dereference-of-error-pointers-in-sti_hqvdp_atomic_check.patch drm-sti-avoid-potential-dereference-of-error-pointers.patch drm-xe-guc_submit-fix-race-around-suspend_pending.patch drm-xe-migrate-fix-pat-index-usage.patch drm-xe-migrate-use-xe_bo_flag_pagetable.patch drm-xe-xe_guc_ads-save-restore-oa-registers-and-allowlist-regs.patch drm-xlnx-zynqmp_dpsub-fix-hotplug-detection.patch revert-drm-radeon-delay-connector-detecting-when-hpd-singals-is-unstable.patch --- diff --git a/queue-6.12/drm-amd-add-some-missing-straps-from-nbio-7.11.0.patch b/queue-6.12/drm-amd-add-some-missing-straps-from-nbio-7.11.0.patch new file mode 100644 index 00000000000..15e506a782b --- /dev/null +++ b/queue-6.12/drm-amd-add-some-missing-straps-from-nbio-7.11.0.patch @@ -0,0 +1,57 @@ +From 902fbbf429b8213232b18de0ddfd5c0f3851cb8f Mon Sep 17 00:00:00 2001 +From: Mario Limonciello +Date: Mon, 18 Nov 2024 11:46:10 -0600 +Subject: drm/amd: Add some missing straps from NBIO 7.11.0 + +From: Mario Limonciello + +commit 902fbbf429b8213232b18de0ddfd5c0f3851cb8f upstream. + +Earlier ASICs have strap information exported, and this is missing +for NBIO 7.11.0. + +Cc: stable@vger.kernel.org +Reviewed-by: Alex Deucher +Fixes: ca8c68142ad8 ("drm/amdgpu: add nbio 7.11 registers") +Link: https://lore.kernel.org/r/20241118174611.10700-1-mario.limonciello@amd.com +Signed-off-by: Mario Limonciello +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_offset.h | 2 + + drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_sh_mask.h | 13 ++++++++++ + 2 files changed, 15 insertions(+) + +--- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_offset.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_offset.h +@@ -7571,6 +7571,8 @@ + // base address: 0x10100000 + #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0 0xd000 + #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_BASE_IDX 5 ++#define regRCC_DEV0_EPF5_STRAP4 0xd284 ++#define regRCC_DEV0_EPF5_STRAP4_BASE_IDX 5 + + + // addressBlock: nbio_nbif0_bif_rst_bif_rst_regblk +--- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_sh_mask.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_sh_mask.h +@@ -50665,6 +50665,19 @@ + #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L + #define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L + ++//RCC_DEV0_EPF5_STRAP4 ++#define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F5__SHIFT 0x14 ++#define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_EN_DEV0_F5__SHIFT 0x15 ++#define RCC_DEV0_EPF5_STRAP4__STRAP_FLR_EN_DEV0_F5__SHIFT 0x16 ++#define RCC_DEV0_EPF5_STRAP4__STRAP_PME_SUPPORT_DEV0_F5__SHIFT 0x17 ++#define RCC_DEV0_EPF5_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F5__SHIFT 0x1c ++#define RCC_DEV0_EPF5_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F5__SHIFT 0x1f ++#define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F5_MASK 0x00100000L ++#define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_EN_DEV0_F5_MASK 0x00200000L ++#define RCC_DEV0_EPF5_STRAP4__STRAP_FLR_EN_DEV0_F5_MASK 0x00400000L ++#define RCC_DEV0_EPF5_STRAP4__STRAP_PME_SUPPORT_DEV0_F5_MASK 0x0F800000L ++#define RCC_DEV0_EPF5_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F5_MASK 0x70000000L ++#define RCC_DEV0_EPF5_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F5_MASK 0x80000000L + + // addressBlock: nbio_nbif0_bif_rst_bif_rst_regblk + //HARD_RST_CTRL diff --git a/queue-6.12/drm-amd-display-fix-handling-of-plane-refcount.patch b/queue-6.12/drm-amd-display-fix-handling-of-plane-refcount.patch new file mode 100644 index 00000000000..d378ed83565 --- /dev/null +++ b/queue-6.12/drm-amd-display-fix-handling-of-plane-refcount.patch @@ -0,0 +1,43 @@ +From 27227a234c1487cb7a684615f0749c455218833a Mon Sep 17 00:00:00 2001 +From: Joshua Aberback +Date: Mon, 28 Oct 2024 17:12:22 -0400 +Subject: drm/amd/display: Fix handling of plane refcount + +From: Joshua Aberback + +commit 27227a234c1487cb7a684615f0749c455218833a upstream. + +[Why] +The mechanism to backup and restore plane states doesn't maintain +refcount, which can cause issues if the refcount of the plane changes +in between backup and restore operations, such as memory leaks if the +refcount was supposed to go down, or double frees / invalid memory +accesses if the refcount was supposed to go up. + +[How] +Cache and re-apply current refcount when restoring plane states. + +Cc: stable@vger.kernel.org +Reviewed-by: Josip Pavic +Signed-off-by: Joshua Aberback +Signed-off-by: Hamza Mahfooz +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/dc/core/dc.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -3066,7 +3066,10 @@ static void restore_planes_and_stream_st + return; + + for (i = 0; i < status->plane_count; i++) { ++ /* refcount will always be valid, restore everything else */ ++ struct kref refcount = status->plane_states[i]->refcount; + *status->plane_states[i] = scratch->plane_states[i]; ++ status->plane_states[i]->refcount = refcount; + } + *stream = scratch->stream_state; + } diff --git a/queue-6.12/drm-amd-display-remove-pipe_dto_src_sel-programming-from-set_dtbclk_dto.patch b/queue-6.12/drm-amd-display-remove-pipe_dto_src_sel-programming-from-set_dtbclk_dto.patch new file mode 100644 index 00000000000..fccce1c59e0 --- /dev/null +++ b/queue-6.12/drm-amd-display-remove-pipe_dto_src_sel-programming-from-set_dtbclk_dto.patch @@ -0,0 +1,68 @@ +From a3e6079bd93d5c66a43bf6a5f90e5b98465dc7b3 Mon Sep 17 00:00:00 2001 +From: Ovidiu Bunea +Date: Wed, 6 Nov 2024 16:25:18 -0500 +Subject: drm/amd/display: Remove PIPE_DTO_SRC_SEL programming from set_dtbclk_dto + +From: Ovidiu Bunea + +commit a3e6079bd93d5c66a43bf6a5f90e5b98465dc7b3 upstream. + +There are cases where an OTG is remapped from driving a regular HDMI +display to a DP/eDP display. There are also cases where DTBCLK needs to +be enabled for HPO, but DTBCLK DTO programming may be done while OTG is +still enabled which is dangerous as the PIPE_DTO_SRC_SEL programming may +change the pixel clock generator source for a mapped and running OTG and +cause it to hang. + +Remove the PIPE_DTO_SRC_SEL programming from this sequence since it is +already done in program_pixel_clk(). Additionally, make sure that +program_pixel_clk sets DTBCLK DTO as source for special HDMI cases. + +Cc: stable@vger.kernel.org # 6.11+ +Reviewed-by: Nicholas Kazlauskas +Signed-off-by: Ovidiu Bunea +Signed-off-by: Hamza Mahfooz +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman +--- + .../drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c | 15 +++++++++------ + 1 file changed, 9 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c +index 838d72eaa87f..b363f5360818 100644 +--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c ++++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c +@@ -1392,10 +1392,10 @@ static void dccg35_set_dtbclk_dto( + + /* The recommended programming sequence to enable DTBCLK DTO to generate + * valid pixel HPO DPSTREAM ENCODER, specifies that DTO source select should +- * be set only after DTO is enabled ++ * be set only after DTO is enabled. ++ * PIPEx_DTO_SRC_SEL should not be programmed during DTBCLK update since OTG may still be on, and the ++ * programming is handled in program_pix_clk() regardless, so it can be removed from here. + */ +- REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst], +- PIPE_DTO_SRC_SEL[params->otg_inst], 2); + } else { + switch (params->otg_inst) { + case 0: +@@ -1412,9 +1412,12 @@ static void dccg35_set_dtbclk_dto( + break; + } + +- REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[params->otg_inst], +- DTBCLK_DTO_ENABLE[params->otg_inst], 0, +- PIPE_DTO_SRC_SEL[params->otg_inst], params->is_hdmi ? 0 : 1); ++ /** ++ * PIPEx_DTO_SRC_SEL should not be programmed during DTBCLK update since OTG may still be on, and the ++ * programming is handled in program_pix_clk() regardless, so it can be removed from here. ++ */ ++ REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst], ++ DTBCLK_DTO_ENABLE[params->otg_inst], 0); + + REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], 0); + REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], 0); +-- +2.47.1 + diff --git a/queue-6.12/drm-amd-display-update-pipe-selection-policy-to-check-head-pipe.patch b/queue-6.12/drm-amd-display-update-pipe-selection-policy-to-check-head-pipe.patch new file mode 100644 index 00000000000..be7d3dba15b --- /dev/null +++ b/queue-6.12/drm-amd-display-update-pipe-selection-policy-to-check-head-pipe.patch @@ -0,0 +1,73 @@ +From 8fef253c94a5312b9150b2ff8e633b331bac7e88 Mon Sep 17 00:00:00 2001 +From: Yihan Zhu +Date: Wed, 30 Oct 2024 16:20:21 -0400 +Subject: drm/amd/display: update pipe selection policy to check head pipe + +From: Yihan Zhu + +commit 8fef253c94a5312b9150b2ff8e633b331bac7e88 upstream. + +[Why] +No check on head pipe during the dml to dc hw mapping will allow illegal +pipe usage. This will result in a wrong pipe topology to cause mpcc tree +totally mess up then cause a display hang. + +[How] +Avoid to use the pipe is head in all check and avoid ODM slice during +preferred pipe check. + +Cc: stable@vger.kernel.org +Reviewed-by: Nicholas Kazlauskas +Signed-off-by: Yihan Zhu +Signed-off-by: Hamza Mahfooz +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c | 23 +++++++++++- + 1 file changed, 22 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c ++++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c +@@ -258,12 +258,25 @@ static unsigned int find_preferred_pipe_ + * However this condition comes with a caveat. We need to ignore pipes that will + * require a change in OPP but still have the same stream id. For example during + * an MPC to ODM transiton. ++ * ++ * Adding check to avoid pipe select on the head pipe by utilizing dc resource ++ * helper function resource_get_primary_dpp_pipe and comparing the pipe index. + */ + if (existing_state) { + for (i = 0; i < pipe_count; i++) { + if (existing_state->res_ctx.pipe_ctx[i].stream && existing_state->res_ctx.pipe_ctx[i].stream->stream_id == stream_id) { ++ struct pipe_ctx *head_pipe = ++ resource_is_pipe_type(&existing_state->res_ctx.pipe_ctx[i], DPP_PIPE) ? ++ resource_get_primary_dpp_pipe(&existing_state->res_ctx.pipe_ctx[i]) : ++ NULL; ++ ++ // we should always respect the head pipe from selection ++ if (head_pipe && head_pipe->pipe_idx == i) ++ continue; + if (existing_state->res_ctx.pipe_ctx[i].plane_res.hubp && +- existing_state->res_ctx.pipe_ctx[i].plane_res.hubp->opp_id != i) ++ existing_state->res_ctx.pipe_ctx[i].plane_res.hubp->opp_id != i && ++ (existing_state->res_ctx.pipe_ctx[i].prev_odm_pipe || ++ existing_state->res_ctx.pipe_ctx[i].next_odm_pipe)) + continue; + + preferred_pipe_candidates[num_preferred_candidates++] = i; +@@ -292,6 +305,14 @@ static unsigned int find_last_resort_pip + */ + if (existing_state) { + for (i = 0; i < pipe_count; i++) { ++ struct pipe_ctx *head_pipe = ++ resource_is_pipe_type(&existing_state->res_ctx.pipe_ctx[i], DPP_PIPE) ? ++ resource_get_primary_dpp_pipe(&existing_state->res_ctx.pipe_ctx[i]) : ++ NULL; ++ ++ // we should always respect the head pipe from selection ++ if (head_pipe && head_pipe->pipe_idx == i) ++ continue; + if ((existing_state->res_ctx.pipe_ctx[i].plane_res.hubp && + existing_state->res_ctx.pipe_ctx[i].plane_res.hubp->opp_id != i) || + existing_state->res_ctx.pipe_ctx[i].stream_res.tg) diff --git a/queue-6.12/drm-amd-fix-initialization-mistake-for-nbio-7.11-devices.patch b/queue-6.12/drm-amd-fix-initialization-mistake-for-nbio-7.11-devices.patch new file mode 100644 index 00000000000..8177f6f346e --- /dev/null +++ b/queue-6.12/drm-amd-fix-initialization-mistake-for-nbio-7.11-devices.patch @@ -0,0 +1,40 @@ +From 349af06a3abd0bb3787ee2daf3ac508412fe8dcc Mon Sep 17 00:00:00 2001 +From: Mario Limonciello +Date: Mon, 18 Nov 2024 11:46:11 -0600 +Subject: drm/amd: Fix initialization mistake for NBIO 7.11 devices + +From: Mario Limonciello + +commit 349af06a3abd0bb3787ee2daf3ac508412fe8dcc upstream. + +There is a strapping issue on NBIO 7.11.x that can lead to spurious PME +events while in the D0 state. + +Cc: stable@vger.kernel.org +Reviewed-by: Alex Deucher +Link: https://lore.kernel.org/r/20241118174611.10700-2-mario.limonciello@amd.com +Signed-off-by: Mario Limonciello +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c ++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c +@@ -275,6 +275,15 @@ static void nbio_v7_11_init_registers(st + if (def != data) + WREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3, data); + ++ switch (adev->ip_versions[NBIO_HWIP][0]) { ++ case IP_VERSION(7, 11, 0): ++ case IP_VERSION(7, 11, 1): ++ case IP_VERSION(7, 11, 2): ++ case IP_VERSION(7, 11, 3): ++ data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF5_STRAP4) & ~BIT(23); ++ WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF5_STRAP4, data); ++ break; ++ } + } + + static void nbio_v7_11_update_medium_grain_clock_gating(struct amdgpu_device *adev, diff --git a/queue-6.12/drm-amd-pm-disable-pcie-speed-switching-on-intel-platform-for-smu-v14.0.2-3.patch b/queue-6.12/drm-amd-pm-disable-pcie-speed-switching-on-intel-platform-for-smu-v14.0.2-3.patch new file mode 100644 index 00000000000..35ec267c090 --- /dev/null +++ b/queue-6.12/drm-amd-pm-disable-pcie-speed-switching-on-intel-platform-for-smu-v14.0.2-3.patch @@ -0,0 +1,63 @@ +From b0df0e777874549c128b43f7bf4989a2ed24b37a Mon Sep 17 00:00:00 2001 +From: Kenneth Feng +Date: Tue, 19 Nov 2024 14:26:58 +0800 +Subject: drm/amd/pm: disable pcie speed switching on Intel platform for smu v14.0.2/3 + +From: Kenneth Feng + +commit b0df0e777874549c128b43f7bf4989a2ed24b37a upstream. + +disable pcie speed switching on Intel platform for smu v14.0.2/3 +based on Intel's requirement. +v2: align the setting with smu v13. + +Signed-off-by: Kenneth Feng +Reviewed-by: Lijo Lazar +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org # 6.11.x +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 26 ++++++++++++++++--- + 1 file changed, 23 insertions(+), 3 deletions(-) + +--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c +@@ -1477,15 +1477,35 @@ static int smu_v14_0_2_update_pcie_param + struct smu_14_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; + struct smu_14_0_pcie_table *pcie_table = + &dpm_context->dpm_tables.pcie_table; ++ int num_of_levels = pcie_table->num_of_link_levels; + uint32_t smu_pcie_arg; + int ret, i; + +- for (i = 0; i < pcie_table->num_of_link_levels; i++) { +- if (pcie_table->pcie_gen[i] > pcie_gen_cap) ++ if (!num_of_levels) ++ return 0; ++ ++ if (!(smu->adev->pm.pp_feature & PP_PCIE_DPM_MASK)) { ++ if (pcie_table->pcie_gen[num_of_levels - 1] < pcie_gen_cap) ++ pcie_gen_cap = pcie_table->pcie_gen[num_of_levels - 1]; ++ ++ if (pcie_table->pcie_lane[num_of_levels - 1] < pcie_width_cap) ++ pcie_width_cap = pcie_table->pcie_lane[num_of_levels - 1]; ++ ++ /* Force all levels to use the same settings */ ++ for (i = 0; i < num_of_levels; i++) { + pcie_table->pcie_gen[i] = pcie_gen_cap; +- if (pcie_table->pcie_lane[i] > pcie_width_cap) + pcie_table->pcie_lane[i] = pcie_width_cap; ++ } ++ } else { ++ for (i = 0; i < num_of_levels; i++) { ++ if (pcie_table->pcie_gen[i] > pcie_gen_cap) ++ pcie_table->pcie_gen[i] = pcie_gen_cap; ++ if (pcie_table->pcie_lane[i] > pcie_width_cap) ++ pcie_table->pcie_lane[i] = pcie_width_cap; ++ } ++ } + ++ for (i = 0; i < num_of_levels; i++) { + smu_pcie_arg = i << 16; + smu_pcie_arg |= pcie_table->pcie_gen[i] << 8; + smu_pcie_arg |= pcie_table->pcie_lane[i]; diff --git a/queue-6.12/drm-amd-pm-remove-arcturus-min-power-limit.patch b/queue-6.12/drm-amd-pm-remove-arcturus-min-power-limit.patch new file mode 100644 index 00000000000..b0ccd290656 --- /dev/null +++ b/queue-6.12/drm-amd-pm-remove-arcturus-min-power-limit.patch @@ -0,0 +1,38 @@ +From da868898cf4c5ddbd1f7406e356edce5d7211eb5 Mon Sep 17 00:00:00 2001 +From: Lijo Lazar +Date: Wed, 20 Nov 2024 08:34:39 +0530 +Subject: drm/amd/pm: Remove arcturus min power limit + +From: Lijo Lazar + +commit da868898cf4c5ddbd1f7406e356edce5d7211eb5 upstream. + +As per power team, there is no need to impose a lower bound on arcturus +power limit. Any unreasonable limit set will result in frequent +throttling. + +Signed-off-by: Lijo Lazar +Reviewed-by: Kenneth Feng +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c +@@ -1344,8 +1344,12 @@ static int arcturus_get_power_limit(stru + *default_power_limit = power_limit; + if (max_power_limit) + *max_power_limit = power_limit; ++ /** ++ * No lower bound is imposed on the limit. Any unreasonable limit set ++ * will result in frequent throttling. ++ */ + if (min_power_limit) +- *min_power_limit = power_limit; ++ *min_power_limit = 0; + + return 0; + } diff --git a/queue-6.12/drm-amd-pm-skip-setting-the-power-source-on-smu-v14.0.2-3.patch b/queue-6.12/drm-amd-pm-skip-setting-the-power-source-on-smu-v14.0.2-3.patch new file mode 100644 index 00000000000..8d7037fd9d0 --- /dev/null +++ b/queue-6.12/drm-amd-pm-skip-setting-the-power-source-on-smu-v14.0.2-3.patch @@ -0,0 +1,30 @@ +From 76c7f08094767b5df3b60e18d1bdecddd4a5c844 Mon Sep 17 00:00:00 2001 +From: Kenneth Feng +Date: Tue, 19 Nov 2024 15:03:22 +0800 +Subject: drm/amd/pm: skip setting the power source on smu v14.0.2/3 + +From: Kenneth Feng + +commit 76c7f08094767b5df3b60e18d1bdecddd4a5c844 upstream. + +skip setting power source on smu v14.0.2/3 + +Signed-off-by: Kenneth Feng +Reviewed-by: Lijo Lazar +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org # 6.11.x +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 1 - + 1 file changed, 1 deletion(-) + +--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c +@@ -2769,7 +2769,6 @@ static const struct pptable_funcs smu_v1 + .get_unique_id = smu_v14_0_2_get_unique_id, + .get_power_limit = smu_v14_0_2_get_power_limit, + .set_power_limit = smu_v14_0_2_set_power_limit, +- .set_power_source = smu_v14_0_set_power_source, + .get_power_profile_mode = smu_v14_0_2_get_power_profile_mode, + .set_power_profile_mode = smu_v14_0_2_set_power_profile_mode, + .run_btc = smu_v14_0_run_btc, diff --git a/queue-6.12/drm-amd-pm-update-current_socclk-and-current_uclk-in-gpu_metrics-on-smu-v13.0.7.patch b/queue-6.12/drm-amd-pm-update-current_socclk-and-current_uclk-in-gpu_metrics-on-smu-v13.0.7.patch new file mode 100644 index 00000000000..580547309bf --- /dev/null +++ b/queue-6.12/drm-amd-pm-update-current_socclk-and-current_uclk-in-gpu_metrics-on-smu-v13.0.7.patch @@ -0,0 +1,31 @@ +From 2abf2f7032df4c4e7f6cf7906da59d0e614897d6 Mon Sep 17 00:00:00 2001 +From: Umio Yasuno +Date: Thu, 14 Nov 2024 16:15:27 +0900 +Subject: drm/amd/pm: update current_socclk and current_uclk in gpu_metrics on smu v13.0.7 + +From: Umio Yasuno + +commit 2abf2f7032df4c4e7f6cf7906da59d0e614897d6 upstream. + +These were missed before. + +Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3751 +Signed-off-by: Umio Yasuno +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +@@ -2061,6 +2061,8 @@ static ssize_t smu_v13_0_7_get_gpu_metri + gpu_metrics->average_dclk1_frequency = metrics->AverageDclk1Frequency; + + gpu_metrics->current_gfxclk = metrics->CurrClock[PPCLK_GFXCLK]; ++ gpu_metrics->current_socclk = metrics->CurrClock[PPCLK_SOCCLK]; ++ gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK]; + gpu_metrics->current_vclk0 = metrics->CurrClock[PPCLK_VCLK_0]; + gpu_metrics->current_dclk0 = metrics->CurrClock[PPCLK_DCLK_0]; + gpu_metrics->current_vclk1 = metrics->CurrClock[PPCLK_VCLK_1]; diff --git a/queue-6.12/drm-amdgpu-fix-usage-slab-after-free.patch b/queue-6.12/drm-amdgpu-fix-usage-slab-after-free.patch new file mode 100644 index 00000000000..a13f40ba069 --- /dev/null +++ b/queue-6.12/drm-amdgpu-fix-usage-slab-after-free.patch @@ -0,0 +1,218 @@ +From b61badd20b443eabe132314669bb51a263982e5c Mon Sep 17 00:00:00 2001 +From: Vitaly Prosyak +Date: Mon, 11 Nov 2024 17:24:08 -0500 +Subject: drm/amdgpu: fix usage slab after free +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Vitaly Prosyak + +commit b61badd20b443eabe132314669bb51a263982e5c upstream. + +[ +0.000021] BUG: KASAN: slab-use-after-free in drm_sched_entity_flush+0x6cb/0x7a0 [gpu_sched] +[ +0.000027] Read of size 8 at addr ffff8881b8605f88 by task amd_pci_unplug/2147 + +[ +0.000023] CPU: 6 PID: 2147 Comm: amd_pci_unplug Not tainted 6.10.0+ #1 +[ +0.000016] Hardware name: ASUS System Product Name/ROG STRIX B550-F GAMING (WI-FI), BIOS 1401 12/03/2020 +[ +0.000016] Call Trace: +[ +0.000008] +[ +0.000009] dump_stack_lvl+0x76/0xa0 +[ +0.000017] print_report+0xce/0x5f0 +[ +0.000017] ? drm_sched_entity_flush+0x6cb/0x7a0 [gpu_sched] +[ +0.000019] ? srso_return_thunk+0x5/0x5f +[ +0.000015] ? kasan_complete_mode_report_info+0x72/0x200 +[ +0.000016] ? drm_sched_entity_flush+0x6cb/0x7a0 [gpu_sched] +[ +0.000019] kasan_report+0xbe/0x110 +[ +0.000015] ? drm_sched_entity_flush+0x6cb/0x7a0 [gpu_sched] +[ +0.000023] __asan_report_load8_noabort+0x14/0x30 +[ +0.000014] drm_sched_entity_flush+0x6cb/0x7a0 [gpu_sched] +[ +0.000020] ? srso_return_thunk+0x5/0x5f +[ +0.000013] ? __kasan_check_write+0x14/0x30 +[ +0.000016] ? __pfx_drm_sched_entity_flush+0x10/0x10 [gpu_sched] +[ +0.000020] ? srso_return_thunk+0x5/0x5f +[ +0.000013] ? __kasan_check_write+0x14/0x30 +[ +0.000013] ? srso_return_thunk+0x5/0x5f +[ +0.000013] ? enable_work+0x124/0x220 +[ +0.000015] ? __pfx_enable_work+0x10/0x10 +[ +0.000013] ? srso_return_thunk+0x5/0x5f +[ +0.000014] ? free_large_kmalloc+0x85/0xf0 +[ +0.000016] drm_sched_entity_destroy+0x18/0x30 [gpu_sched] +[ +0.000020] amdgpu_vce_sw_fini+0x55/0x170 [amdgpu] +[ +0.000735] ? __kasan_check_read+0x11/0x20 +[ +0.000016] vce_v4_0_sw_fini+0x80/0x110 [amdgpu] +[ +0.000726] amdgpu_device_fini_sw+0x331/0xfc0 [amdgpu] +[ +0.000679] ? mutex_unlock+0x80/0xe0 +[ +0.000017] ? __pfx_amdgpu_device_fini_sw+0x10/0x10 [amdgpu] +[ +0.000662] ? srso_return_thunk+0x5/0x5f +[ +0.000014] ? __kasan_check_write+0x14/0x30 +[ +0.000013] ? srso_return_thunk+0x5/0x5f +[ +0.000013] ? mutex_unlock+0x80/0xe0 +[ +0.000016] amdgpu_driver_release_kms+0x16/0x80 [amdgpu] +[ +0.000663] drm_minor_release+0xc9/0x140 [drm] +[ +0.000081] drm_release+0x1fd/0x390 [drm] +[ +0.000082] __fput+0x36c/0xad0 +[ +0.000018] __fput_sync+0x3c/0x50 +[ +0.000014] __x64_sys_close+0x7d/0xe0 +[ +0.000014] x64_sys_call+0x1bc6/0x2680 +[ +0.000014] do_syscall_64+0x70/0x130 +[ +0.000014] ? srso_return_thunk+0x5/0x5f +[ +0.000014] ? irqentry_exit_to_user_mode+0x60/0x190 +[ +0.000015] ? srso_return_thunk+0x5/0x5f +[ +0.000014] ? irqentry_exit+0x43/0x50 +[ +0.000012] ? srso_return_thunk+0x5/0x5f +[ +0.000013] ? exc_page_fault+0x7c/0x110 +[ +0.000015] entry_SYSCALL_64_after_hwframe+0x76/0x7e +[ +0.000014] RIP: 0033:0x7ffff7b14f67 +[ +0.000013] Code: ff e8 0d 16 02 00 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 00 f3 0f 1e fa 64 8b 04 25 18 00 00 00 85 c0 75 10 b8 03 00 00 00 0f 05 <48> 3d 00 f0 ff ff 77 41 c3 48 83 ec 18 89 7c 24 0c e8 73 ba f7 ff +[ +0.000026] RSP: 002b:00007fffffffe378 EFLAGS: 00000246 ORIG_RAX: 0000000000000003 +[ +0.000019] RAX: ffffffffffffffda RBX: 0000000000000000 RCX: 00007ffff7b14f67 +[ +0.000014] RDX: 0000000000000000 RSI: 00007ffff7f6f47a RDI: 0000000000000003 +[ +0.000014] RBP: 00007fffffffe3a0 R08: 0000555555569890 R09: 0000000000000000 +[ +0.000014] R10: 0000000000000000 R11: 0000000000000246 R12: 00007fffffffe5c8 +[ +0.000013] R13: 00005555555552a9 R14: 0000555555557d48 R15: 00007ffff7ffd040 +[ +0.000020] + +[ +0.000016] Allocated by task 383 on cpu 7 at 26.880319s: +[ +0.000014] kasan_save_stack+0x28/0x60 +[ +0.000008] kasan_save_track+0x18/0x70 +[ +0.000007] kasan_save_alloc_info+0x38/0x60 +[ +0.000007] __kasan_kmalloc+0xc1/0xd0 +[ +0.000007] kmalloc_trace_noprof+0x180/0x380 +[ +0.000007] drm_sched_init+0x411/0xec0 [gpu_sched] +[ +0.000012] amdgpu_device_init+0x695f/0xa610 [amdgpu] +[ +0.000658] amdgpu_driver_load_kms+0x1a/0x120 [amdgpu] +[ +0.000662] amdgpu_pci_probe+0x361/0xf30 [amdgpu] +[ +0.000651] local_pci_probe+0xe7/0x1b0 +[ +0.000009] pci_device_probe+0x248/0x890 +[ +0.000008] really_probe+0x1fd/0x950 +[ +0.000008] __driver_probe_device+0x307/0x410 +[ +0.000007] driver_probe_device+0x4e/0x150 +[ +0.000007] __driver_attach+0x223/0x510 +[ +0.000006] bus_for_each_dev+0x102/0x1a0 +[ +0.000007] driver_attach+0x3d/0x60 +[ +0.000006] bus_add_driver+0x2ac/0x5f0 +[ +0.000006] driver_register+0x13d/0x490 +[ +0.000008] __pci_register_driver+0x1ee/0x2b0 +[ +0.000007] llc_sap_close+0xb0/0x160 [llc] +[ +0.000009] do_one_initcall+0x9c/0x3e0 +[ +0.000008] do_init_module+0x241/0x760 +[ +0.000008] load_module+0x51ac/0x6c30 +[ +0.000006] __do_sys_init_module+0x234/0x270 +[ +0.000007] __x64_sys_init_module+0x73/0xc0 +[ +0.000006] x64_sys_call+0xe3/0x2680 +[ +0.000006] do_syscall_64+0x70/0x130 +[ +0.000007] entry_SYSCALL_64_after_hwframe+0x76/0x7e + +[ +0.000015] Freed by task 2147 on cpu 6 at 160.507651s: +[ +0.000013] kasan_save_stack+0x28/0x60 +[ +0.000007] kasan_save_track+0x18/0x70 +[ +0.000007] kasan_save_free_info+0x3b/0x60 +[ +0.000007] poison_slab_object+0x115/0x1c0 +[ +0.000007] __kasan_slab_free+0x34/0x60 +[ +0.000007] kfree+0xfa/0x2f0 +[ +0.000007] drm_sched_fini+0x19d/0x410 [gpu_sched] +[ +0.000012] amdgpu_fence_driver_sw_fini+0xc4/0x2f0 [amdgpu] +[ +0.000662] amdgpu_device_fini_sw+0x77/0xfc0 [amdgpu] +[ +0.000653] amdgpu_driver_release_kms+0x16/0x80 [amdgpu] +[ +0.000655] drm_minor_release+0xc9/0x140 [drm] +[ +0.000071] drm_release+0x1fd/0x390 [drm] +[ +0.000071] __fput+0x36c/0xad0 +[ +0.000008] __fput_sync+0x3c/0x50 +[ +0.000007] __x64_sys_close+0x7d/0xe0 +[ +0.000007] x64_sys_call+0x1bc6/0x2680 +[ +0.000007] do_syscall_64+0x70/0x130 +[ +0.000007] entry_SYSCALL_64_after_hwframe+0x76/0x7e + +[ +0.000014] The buggy address belongs to the object at ffff8881b8605f80 + which belongs to the cache kmalloc-64 of size 64 +[ +0.000020] The buggy address is located 8 bytes inside of + freed 64-byte region [ffff8881b8605f80, ffff8881b8605fc0) + +[ +0.000028] The buggy address belongs to the physical page: +[ +0.000011] page: refcount:1 mapcount:0 mapping:0000000000000000 index:0x0 pfn:0x1b8605 +[ +0.000008] anon flags: 0x17ffffc0000000(node=0|zone=2|lastcpupid=0x1fffff) +[ +0.000007] page_type: 0xffffefff(slab) +[ +0.000009] raw: 0017ffffc0000000 ffff8881000428c0 0000000000000000 dead000000000001 +[ +0.000006] raw: 0000000000000000 0000000000200020 00000001ffffefff 0000000000000000 +[ +0.000006] page dumped because: kasan: bad access detected + +[ +0.000012] Memory state around the buggy address: +[ +0.000011] ffff8881b8605e80: fa fb fb fb fb fb fb fb fc fc fc fc fc fc fc fc +[ +0.000015] ffff8881b8605f00: 00 00 00 00 00 00 00 00 fc fc fc fc fc fc fc fc +[ +0.000015] >ffff8881b8605f80: fa fb fb fb fb fb fb fb fc fc fc fc fc fc fc fc +[ +0.000013] ^ +[ +0.000011] ffff8881b8606000: fa fb fb fb fb fb fb fb fb fb fb fb fb fb fb fc +[ +0.000014] ffff8881b8606080: fc fc fc fc fc fc fc fa fb fb fb fb fb fb fb fb +[ +0.000013] ================================================================== + +The issue reproduced on VG20 during the IGT pci_unplug test. +The root cause of the issue is that the function drm_sched_fini is called before drm_sched_entity_kill. +In drm_sched_fini, the drm_sched_rq structure is freed, but this structure is later accessed by +each entity within the run queue, leading to invalid memory access. +To resolve this, the order of cleanup calls is updated: + + Before: + amdgpu_fence_driver_sw_fini + amdgpu_device_ip_fini + + After: + amdgpu_device_ip_fini + amdgpu_fence_driver_sw_fini + +This updated order ensures that all entities in the IPs are cleaned up first, followed by proper +cleanup of the schedulers. + +Additional Investigation: + +During debugging, another issue was identified in the amdgpu_vce_sw_fini function. The vce.vcpu_bo +buffer must be freed only as the final step in the cleanup process to prevent any premature +access during earlier cleanup stages. + +v2: Using Christian suggestion call drm_sched_entity_destroy before drm_sched_fini. + +Cc: Christian König +Cc: Alex Deucher +Signed-off-by: Vitaly Prosyak +Reviewed-by: Christian König +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- + drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 6 +++--- + 2 files changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +@@ -4584,8 +4584,8 @@ void amdgpu_device_fini_sw(struct amdgpu + int idx; + bool px; + +- amdgpu_fence_driver_sw_fini(adev); + amdgpu_device_ip_fini(adev); ++ amdgpu_fence_driver_sw_fini(adev); + amdgpu_ucode_release(&adev->firmware.gpu_info_fw); + adev->accel_working = false; + dma_fence_put(rcu_dereference_protected(adev->gang_submit, true)); +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +@@ -214,15 +214,15 @@ int amdgpu_vce_sw_fini(struct amdgpu_dev + + drm_sched_entity_destroy(&adev->vce.entity); + +- amdgpu_bo_free_kernel(&adev->vce.vcpu_bo, &adev->vce.gpu_addr, +- (void **)&adev->vce.cpu_addr); +- + for (i = 0; i < adev->vce.num_rings; i++) + amdgpu_ring_fini(&adev->vce.ring[i]); + + amdgpu_ucode_release(&adev->vce.fw); + mutex_destroy(&adev->vce.idle_mutex); + ++ amdgpu_bo_free_kernel(&adev->vce.vcpu_bo, &adev->vce.gpu_addr, ++ (void **)&adev->vce.cpu_addr); ++ + return 0; + } + diff --git a/queue-6.12/drm-amdgpu-pm-add-gen5-display-to-the-user-on-smu-v14.0.2-3.patch b/queue-6.12/drm-amdgpu-pm-add-gen5-display-to-the-user-on-smu-v14.0.2-3.patch new file mode 100644 index 00000000000..588482a3f81 --- /dev/null +++ b/queue-6.12/drm-amdgpu-pm-add-gen5-display-to-the-user-on-smu-v14.0.2-3.patch @@ -0,0 +1,89 @@ +From 6719ab8234ce4b0c0e9aa93aaa94961e5b2bc852 Mon Sep 17 00:00:00 2001 +From: Kenneth Feng +Date: Tue, 19 Nov 2024 11:10:47 +0800 +Subject: drm/amdgpu/pm: add gen5 display to the user on smu v14.0.2/3 + +From: Kenneth Feng + +commit 6719ab8234ce4b0c0e9aa93aaa94961e5b2bc852 upstream. + +add gen5 display to the user on smu v14.0.2/3 + +Signed-off-by: Kenneth Feng +Reviewed-by: Yang Wang +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org # 6.11.x +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 8 ++++++-- + drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h | 2 +- + drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c | 2 +- + drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 6 ++++-- + 4 files changed, 12 insertions(+), 6 deletions(-) + +--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +@@ -1695,7 +1695,9 @@ static int smu_smc_hw_setup(struct smu_c + return ret; + } + +- if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) ++ if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5) ++ pcie_gen = 4; ++ else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) + pcie_gen = 3; + else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) + pcie_gen = 2; +@@ -1708,7 +1710,9 @@ static int smu_smc_hw_setup(struct smu_c + * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 + * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 + */ +- if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) ++ if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32) ++ pcie_width = 7; ++ else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) + pcie_width = 6; + else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) + pcie_width = 5; +--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h ++++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h +@@ -53,7 +53,7 @@ + #define CTF_OFFSET_MEM 5 + + extern const int decoded_link_speed[5]; +-extern const int decoded_link_width[7]; ++extern const int decoded_link_width[8]; + + #define DECODE_GEN_SPEED(gen_speed_idx) (decoded_link_speed[gen_speed_idx]) + #define DECODE_LANE_WIDTH(lane_width_idx) (decoded_link_width[lane_width_idx]) +--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c +@@ -49,7 +49,7 @@ + #define regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0_BASE_IDX 0 + + const int decoded_link_speed[5] = {1, 2, 3, 4, 5}; +-const int decoded_link_width[7] = {0, 1, 2, 4, 8, 12, 16}; ++const int decoded_link_width[8] = {0, 1, 2, 4, 8, 12, 16, 32}; + /* + * DO NOT use these for err/warn/info/debug messages. + * Use dev_err, dev_warn, dev_info and dev_dbg instead. +--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c +@@ -1186,13 +1186,15 @@ static int smu_v14_0_2_print_clk_levels( + (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s," : + (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s," : + (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s," : +- (pcie_table->pcie_gen[i] == 3) ? "16.0GT/s," : "", ++ (pcie_table->pcie_gen[i] == 3) ? "16.0GT/s," : ++ (pcie_table->pcie_gen[i] == 4) ? "32.0GT/s," : "", + (pcie_table->pcie_lane[i] == 1) ? "x1" : + (pcie_table->pcie_lane[i] == 2) ? "x2" : + (pcie_table->pcie_lane[i] == 3) ? "x4" : + (pcie_table->pcie_lane[i] == 4) ? "x8" : + (pcie_table->pcie_lane[i] == 5) ? "x12" : +- (pcie_table->pcie_lane[i] == 6) ? "x16" : "", ++ (pcie_table->pcie_lane[i] == 6) ? "x16" : ++ (pcie_table->pcie_lane[i] == 7) ? "x32" : "", + pcie_table->clk_freq[i], + (gen_speed == DECODE_GEN_SPEED(pcie_table->pcie_gen[i])) && + (lane_width == DECODE_LANE_WIDTH(pcie_table->pcie_lane[i])) ? diff --git a/queue-6.12/drm-amdkfd-use-the-correct-wptr-size.patch b/queue-6.12/drm-amdkfd-use-the-correct-wptr-size.patch new file mode 100644 index 00000000000..189e19ea41b --- /dev/null +++ b/queue-6.12/drm-amdkfd-use-the-correct-wptr-size.patch @@ -0,0 +1,32 @@ +From cdc6705f98ea3f854a60ba8c9b19228e197ae384 Mon Sep 17 00:00:00 2001 +From: Lijo Lazar +Date: Mon, 11 Nov 2024 20:11:38 +0530 +Subject: drm/amdkfd: Use the correct wptr size + +From: Lijo Lazar + +commit cdc6705f98ea3f854a60ba8c9b19228e197ae384 upstream. + +Write pointer could be 32-bit or 64-bit. Use the correct size during +initialization. + +Signed-off-by: Lijo Lazar +Acked-by: Alex Deucher +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c ++++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c +@@ -125,7 +125,7 @@ static bool kq_initialize(struct kernel_ + + memset(kq->pq_kernel_addr, 0, queue_size); + memset(kq->rptr_kernel, 0, sizeof(*kq->rptr_kernel)); +- memset(kq->wptr_kernel, 0, sizeof(*kq->wptr_kernel)); ++ memset(kq->wptr_kernel, 0, dev->kfd->device_info.doorbell_size); + + prop.queue_size = queue_size; + prop.is_interop = false; diff --git a/queue-6.12/drm-bridge-it6505-fix-inverted-reset-polarity.patch b/queue-6.12/drm-bridge-it6505-fix-inverted-reset-polarity.patch new file mode 100644 index 00000000000..1c95c75b200 --- /dev/null +++ b/queue-6.12/drm-bridge-it6505-fix-inverted-reset-polarity.patch @@ -0,0 +1,69 @@ +From c5f3f21728b069412e8072b8b1d0a3d9d3ab0265 Mon Sep 17 00:00:00 2001 +From: Chen-Yu Tsai +Date: Tue, 29 Oct 2024 17:54:10 +0800 +Subject: drm/bridge: it6505: Fix inverted reset polarity + +From: Chen-Yu Tsai + +commit c5f3f21728b069412e8072b8b1d0a3d9d3ab0265 upstream. + +The IT6505 bridge chip has a active low reset line. Since it is a +"reset" and not an "enable" line, the GPIO should be asserted to +put it in reset and deasserted to bring it out of reset during +the power on sequence. + +The polarity was inverted when the driver was first introduced, likely +because the device family that was targeted had an inverting level +shifter on the reset line. + +The MT8186 Corsola devices already have the IT6505 in their device tree, +but the whole display pipeline is actually disabled and won't be enabled +until some remaining issues are sorted out. The other known user is +the MT8183 Kukui / Jacuzzi family; their device trees currently do not +have the IT6505 included. + +Fix the polarity in the driver while there are no actual users. + +Fixes: b5c84a9edcd4 ("drm/bridge: add it6505 driver") +Cc: stable@vger.kernel.org +Reviewed-by: Dmitry Baryshkov +Reviewed-by: Neil Armstrong +Link: https://patchwork.freedesktop.org/patch/msgid/20241029095411.657616-1-wenst@chromium.org +Signed-off-by: Chen-Yu Tsai +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/bridge/ite-it6505.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/gpu/drm/bridge/ite-it6505.c ++++ b/drivers/gpu/drm/bridge/ite-it6505.c +@@ -2614,9 +2614,9 @@ static int it6505_poweron(struct it6505 + /* time interval between OVDD and SYSRSTN at least be 10ms */ + if (pdata->gpiod_reset) { + usleep_range(10000, 20000); +- gpiod_set_value_cansleep(pdata->gpiod_reset, 0); +- usleep_range(1000, 2000); + gpiod_set_value_cansleep(pdata->gpiod_reset, 1); ++ usleep_range(1000, 2000); ++ gpiod_set_value_cansleep(pdata->gpiod_reset, 0); + usleep_range(25000, 35000); + } + +@@ -2647,7 +2647,7 @@ static int it6505_poweroff(struct it6505 + disable_irq_nosync(it6505->irq); + + if (pdata->gpiod_reset) +- gpiod_set_value_cansleep(pdata->gpiod_reset, 0); ++ gpiod_set_value_cansleep(pdata->gpiod_reset, 1); + + if (pdata->pwr18) { + err = regulator_disable(pdata->pwr18); +@@ -3135,7 +3135,7 @@ static int it6505_init_pdata(struct it65 + return PTR_ERR(pdata->ovdd); + } + +- pdata->gpiod_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); ++ pdata->gpiod_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(pdata->gpiod_reset)) { + dev_err(dev, "gpiod_reset gpio not found"); + return PTR_ERR(pdata->gpiod_reset); diff --git a/queue-6.12/drm-etnaviv-flush-shader-l1-cache-after-user-commandstream.patch b/queue-6.12/drm-etnaviv-flush-shader-l1-cache-after-user-commandstream.patch new file mode 100644 index 00000000000..1fe96350a87 --- /dev/null +++ b/queue-6.12/drm-etnaviv-flush-shader-l1-cache-after-user-commandstream.patch @@ -0,0 +1,33 @@ +From 4f8dbadef085ab447a01a8d4806a3f629fea05ed Mon Sep 17 00:00:00 2001 +From: Lucas Stach +Date: Fri, 25 Oct 2024 17:14:46 +0200 +Subject: drm/etnaviv: flush shader L1 cache after user commandstream + +From: Lucas Stach + +commit 4f8dbadef085ab447a01a8d4806a3f629fea05ed upstream. + +The shader L1 cache is a writeback cache for shader loads/stores +and thus must be flushed before any BOs backing the shader buffers +are potentially freed. + +Cc: stable@vger.kernel.org +Reviewed-by: Christian Gmeiner +Signed-off-by: Lucas Stach +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/etnaviv/etnaviv_buffer.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/etnaviv/etnaviv_buffer.c ++++ b/drivers/gpu/drm/etnaviv/etnaviv_buffer.c +@@ -482,7 +482,8 @@ void etnaviv_buffer_queue(struct etnaviv + } else { + CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_CACHE, + VIVS_GL_FLUSH_CACHE_DEPTH | +- VIVS_GL_FLUSH_CACHE_COLOR); ++ VIVS_GL_FLUSH_CACHE_COLOR | ++ VIVS_GL_FLUSH_CACHE_SHADER_L1); + if (has_blt) { + CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x1); + CMD_LOAD_STATE(buffer, VIVS_BLT_SET_COMMAND, 0x1); diff --git a/queue-6.12/drm-fbdev-dma-select-fb_deferred_io.patch b/queue-6.12/drm-fbdev-dma-select-fb_deferred_io.patch new file mode 100644 index 00000000000..2219d282331 --- /dev/null +++ b/queue-6.12/drm-fbdev-dma-select-fb_deferred_io.patch @@ -0,0 +1,54 @@ +From 67c40c9b2ec5f375bf78274d4e9ef0e3b8315bea Mon Sep 17 00:00:00 2001 +From: Thomas Zimmermann +Date: Mon, 14 Oct 2024 10:55:17 +0200 +Subject: drm/fbdev-dma: Select FB_DEFERRED_IO + +From: Thomas Zimmermann + +commit 67c40c9b2ec5f375bf78274d4e9ef0e3b8315bea upstream. + +Commit 808a40b69468 ("drm/fbdev-dma: Implement damage handling and +deferred I/O") added deferred I/O for fbdev-dma. Also select the +Kconfig symbol FB_DEFERRED_IO (via FB_DMAMEM_HELPERS_DEFERRED). Fixes +build errors about missing fbdefio, such as + +drivers/gpu/drm/drm_fbdev_dma.c:218:26: error: 'struct drm_fb_helper' has no member named 'fbdefio' + 218 | fb_helper->fbdefio.delay = HZ / 20; + | ^~ +drivers/gpu/drm/drm_fbdev_dma.c:219:26: error: 'struct drm_fb_helper' has no member named 'fbdefio' + 219 | fb_helper->fbdefio.deferred_io = drm_fb_helper_deferred_io; + | ^~ +drivers/gpu/drm/drm_fbdev_dma.c:221:21: error: 'struct fb_info' has no member named 'fbdefio' + 221 | info->fbdefio = &fb_helper->fbdefio; + | ^~ +drivers/gpu/drm/drm_fbdev_dma.c:221:43: error: 'struct drm_fb_helper' has no member named 'fbdefio' + 221 | info->fbdefio = &fb_helper->fbdefio; + | ^~ + +Signed-off-by: Thomas Zimmermann +Reported-by: kernel test robot +Closes: https://lore.kernel.org/oe-kbuild-all/202410050241.Mox9QRjP-lkp@intel.com/ +Fixes: 808a40b69468 ("drm/fbdev-dma: Implement damage handling and deferred I/O") +Cc: Thomas Zimmermann +Cc: Javier Martinez Canillas +Cc: Maarten Lankhorst +Cc: Maxime Ripard +Cc: # v6.11+ +Reviewed-by: Jonathan Cavitt +Link: https://patchwork.freedesktop.org/patch/msgid/20241014085740.582287-4-tzimmermann@suse.de +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/Kconfig ++++ b/drivers/gpu/drm/Kconfig +@@ -327,7 +327,7 @@ config DRM_TTM_HELPER + config DRM_GEM_DMA_HELPER + tristate + depends on DRM +- select FB_DMAMEM_HELPERS if DRM_FBDEV_EMULATION ++ select FB_DMAMEM_HELPERS_DEFERRED if DRM_FBDEV_EMULATION + help + Choose this if you need the GEM DMA helper functions + diff --git a/queue-6.12/drm-mediatek-fix-child-node-refcount-handling-in-early-exit.patch b/queue-6.12/drm-mediatek-fix-child-node-refcount-handling-in-early-exit.patch new file mode 100644 index 00000000000..3fef9cea879 --- /dev/null +++ b/queue-6.12/drm-mediatek-fix-child-node-refcount-handling-in-early-exit.patch @@ -0,0 +1,43 @@ +From f708e8b4cfd16e5c8cd8d7fcfcb2fb2c6ed93af3 Mon Sep 17 00:00:00 2001 +From: Javier Carrasco +Date: Fri, 11 Oct 2024 21:21:51 +0200 +Subject: drm/mediatek: Fix child node refcount handling in early exit + +From: Javier Carrasco + +commit f708e8b4cfd16e5c8cd8d7fcfcb2fb2c6ed93af3 upstream. + +Early exits (goto, break, return) from for_each_child_of_node() required +an explicit call to of_node_put(), which was not introduced with the +break if cnt == MAX_CRTC. + +Add the missing of_node_put() before the break. + +Cc: stable@vger.kernel.org +Fixes: d761b9450e31 ("drm/mediatek: Add cnt checking for coverity issue") + +Signed-off-by: Javier Carrasco +Reviewed-by: CK Hu +Reviewed-by: Chen-Yu Tsai +Reviewed-by: AngeloGioacchino Del Regno +Link: https://patchwork.kernel.org/project/dri-devel/patch/20241011-mtk_drm_drv_memleak-v1-1-2b40c74c8d75@gmail.com/ +Signed-off-by: Chun-Kuang Hu +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c ++++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c +@@ -405,8 +405,10 @@ static bool mtk_drm_get_all_drm_priv(str + if (temp_drm_priv->mtk_drm_bound) + cnt++; + +- if (cnt == MAX_CRTC) ++ if (cnt == MAX_CRTC) { ++ of_node_put(node); + break; ++ } + } + + if (drm_priv->data->mmsys_dev_num == cnt) { diff --git a/queue-6.12/drm-panel-jd9365da-h3-remove-unused-num_init_cmds-structure-member.patch b/queue-6.12/drm-panel-jd9365da-h3-remove-unused-num_init_cmds-structure-member.patch new file mode 100644 index 00000000000..a816a006314 --- /dev/null +++ b/queue-6.12/drm-panel-jd9365da-h3-remove-unused-num_init_cmds-structure-member.patch @@ -0,0 +1,35 @@ +From 66ae275365be4f118abe2254a0ced1d913af93f2 Mon Sep 17 00:00:00 2001 +From: Hugo Villeneuve +Date: Mon, 30 Sep 2024 13:05:03 -0400 +Subject: drm: panel: jd9365da-h3: Remove unused num_init_cmds structure member + +From: Hugo Villeneuve + +commit 66ae275365be4f118abe2254a0ced1d913af93f2 upstream. + +Now that the driver has been converted to use wrapped MIPI DCS functions, +the num_init_cmds structure member is no longer needed, so remove it. + +Fixes: 35583e129995 ("drm/panel: panel-jadard-jd9365da-h3: use wrapped MIPI DCS functions") +Cc: stable@vger.kernel.org +Signed-off-by: Hugo Villeneuve +Reviewed-by: Neil Armstrong +Reviewed-by: Jessica Zhang +Link: https://lore.kernel.org/r/20240930170503.1324560-1-hugo@hugovil.com +Signed-off-by: Neil Armstrong +Link: https://patchwork.freedesktop.org/patch/msgid/20240930170503.1324560-1-hugo@hugovil.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c | 1 - + 1 file changed, 1 deletion(-) + +--- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c ++++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c +@@ -26,7 +26,6 @@ struct jadard_panel_desc { + unsigned int lanes; + enum mipi_dsi_pixel_format format; + int (*init)(struct jadard *jadard); +- u32 num_init_cmds; + bool lp11_before_reset; + bool reset_before_power_off_vcioo; + unsigned int vcioo_to_lp11_delay_ms; diff --git a/queue-6.12/drm-panic-fix-uninitialized-spinlock-acquisition-with-config_drm_panic-n.patch b/queue-6.12/drm-panic-fix-uninitialized-spinlock-acquisition-with-config_drm_panic-n.patch new file mode 100644 index 00000000000..4fc566a1e8f --- /dev/null +++ b/queue-6.12/drm-panic-fix-uninitialized-spinlock-acquisition-with-config_drm_panic-n.patch @@ -0,0 +1,164 @@ +From 319e53f155907cf2c6dabc16ec9dce0179bc04d1 Mon Sep 17 00:00:00 2001 +From: Lyude Paul +Date: Mon, 16 Sep 2024 19:00:08 -0400 +Subject: drm/panic: Fix uninitialized spinlock acquisition with CONFIG_DRM_PANIC=n + +From: Lyude Paul + +commit 319e53f155907cf2c6dabc16ec9dce0179bc04d1 upstream. + +It turns out that if you happen to have a kernel config where +CONFIG_DRM_PANIC is disabled and spinlock debugging is enabled, along with +KMS being enabled - we'll end up trying to acquire an uninitialized +spin_lock with drm_panic_lock() when we try to do a commit: + + rvkms rvkms.0: [drm:drm_atomic_commit] committing 0000000068d2ade1 + INFO: trying to register non-static key. + The code is fine but needs lockdep annotation, or maybe + you didn't initialize this object before use? + turning off the locking correctness validator. + CPU: 4 PID: 1347 Comm: modprobe Not tainted 6.10.0-rc1Lyude-Test+ #272 + Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS edk2-20240524-3.fc40 05/24/2024 + Call Trace: + + dump_stack_lvl+0x77/0xa0 + assign_lock_key+0x114/0x120 + register_lock_class+0xa8/0x2c0 + __lock_acquire+0x7d/0x2bd0 + ? __vmap_pages_range_noflush+0x3a8/0x550 + ? drm_atomic_helper_swap_state+0x2ad/0x3a0 + lock_acquire+0xec/0x290 + ? drm_atomic_helper_swap_state+0x2ad/0x3a0 + ? lock_release+0xee/0x310 + _raw_spin_lock_irqsave+0x4e/0x70 + ? drm_atomic_helper_swap_state+0x2ad/0x3a0 + drm_atomic_helper_swap_state+0x2ad/0x3a0 + drm_atomic_helper_commit+0xb1/0x270 + drm_atomic_commit+0xaf/0xe0 + ? __pfx___drm_printfn_info+0x10/0x10 + drm_client_modeset_commit_atomic+0x1a1/0x250 + drm_client_modeset_commit_locked+0x4b/0x180 + drm_client_modeset_commit+0x27/0x50 + __drm_fb_helper_restore_fbdev_mode_unlocked+0x76/0x90 + drm_fb_helper_set_par+0x38/0x40 + fbcon_init+0x3c4/0x690 + visual_init+0xc0/0x120 + do_bind_con_driver+0x409/0x4c0 + do_take_over_console+0x233/0x280 + do_fb_registered+0x11f/0x210 + fbcon_fb_registered+0x2c/0x60 + register_framebuffer+0x248/0x2a0 + __drm_fb_helper_initial_config_and_unlock+0x58a/0x720 + drm_fbdev_generic_client_hotplug+0x6e/0xb0 + drm_client_register+0x76/0xc0 + _RNvXs_CsHeezP08sTT_5rvkmsNtB4_5RvkmsNtNtCs1cdwasc6FUb_6kernel8platform6Driver5probe+0xed2/0x1060 [rvkms] + ? _RNvMs_NtCs1cdwasc6FUb_6kernel8platformINtB4_7AdapterNtCsHeezP08sTT_5rvkms5RvkmsE14probe_callbackBQ_+0x2b/0x70 [rvkms] + ? acpi_dev_pm_attach+0x25/0x110 + ? platform_probe+0x6a/0xa0 + ? really_probe+0x10b/0x400 + ? __driver_probe_device+0x7c/0x140 + ? driver_probe_device+0x22/0x1b0 + ? __device_attach_driver+0x13a/0x1c0 + ? __pfx___device_attach_driver+0x10/0x10 + ? bus_for_each_drv+0x114/0x170 + ? __device_attach+0xd6/0x1b0 + ? bus_probe_device+0x9e/0x120 + ? device_add+0x288/0x4b0 + ? platform_device_add+0x75/0x230 + ? platform_device_register_full+0x141/0x180 + ? rust_helper_platform_device_register_simple+0x85/0xb0 + ? _RNvMs2_NtCs1cdwasc6FUb_6kernel8platformNtB5_6Device13create_simple+0x1d/0x60 + ? _RNvXs0_CsHeezP08sTT_5rvkmsNtB5_5RvkmsNtCs1cdwasc6FUb_6kernel6Module4init+0x11e/0x160 [rvkms] + ? 0xffffffffc083f000 + ? init_module+0x20/0x1000 [rvkms] + ? kernfs_xattr_get+0x3e/0x80 + ? do_one_initcall+0x148/0x3f0 + ? __lock_acquire+0x5ef/0x2bd0 + ? __lock_acquire+0x5ef/0x2bd0 + ? __lock_acquire+0x5ef/0x2bd0 + ? put_cpu_partial+0x51/0x1d0 + ? lock_acquire+0xec/0x290 + ? put_cpu_partial+0x51/0x1d0 + ? lock_release+0xee/0x310 + ? put_cpu_partial+0x51/0x1d0 + ? fs_reclaim_acquire+0x69/0xf0 + ? lock_acquire+0xec/0x290 + ? fs_reclaim_acquire+0x69/0xf0 + ? kfree+0x22f/0x340 + ? lock_release+0xee/0x310 + ? kmalloc_trace_noprof+0x48/0x340 + ? do_init_module+0x22/0x240 + ? kmalloc_trace_noprof+0x155/0x340 + ? do_init_module+0x60/0x240 + ? __se_sys_finit_module+0x2e0/0x3f0 + ? do_syscall_64+0xa4/0x180 + ? syscall_exit_to_user_mode+0x108/0x140 + ? do_syscall_64+0xb0/0x180 + ? vma_end_read+0xd0/0xe0 + ? do_user_addr_fault+0x309/0x640 + ? clear_bhb_loop+0x45/0xa0 + ? clear_bhb_loop+0x45/0xa0 + ? clear_bhb_loop+0x45/0xa0 + ? entry_SYSCALL_64_after_hwframe+0x76/0x7e + + +Fix this by stubbing these macros out when this config option isn't +enabled, along with fixing the unused variable warning that introduces. + +Signed-off-by: Lyude Paul +Reviewed-by: Daniel Vetter +Fixes: e2a1cda3e0c7 ("drm/panic: Add drm panic locking") +Cc: # v6.10+ +Link: https://patchwork.freedesktop.org/patch/msgid/20240916230103.611490-1-lyude@redhat.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/drm_atomic_helper.c | 2 +- + include/drm/drm_panic.h | 14 ++++++++++++++ + 2 files changed, 15 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c +index 43cdf39019a4..5186d2114a50 100644 +--- a/drivers/gpu/drm/drm_atomic_helper.c ++++ b/drivers/gpu/drm/drm_atomic_helper.c +@@ -3015,7 +3015,7 @@ int drm_atomic_helper_swap_state(struct drm_atomic_state *state, + bool stall) + { + int i, ret; +- unsigned long flags; ++ unsigned long flags = 0; + struct drm_connector *connector; + struct drm_connector_state *old_conn_state, *new_conn_state; + struct drm_crtc *crtc; +diff --git a/include/drm/drm_panic.h b/include/drm/drm_panic.h +index 54085d5d05c3..f4e1fa9ae607 100644 +--- a/include/drm/drm_panic.h ++++ b/include/drm/drm_panic.h +@@ -64,6 +64,8 @@ struct drm_scanout_buffer { + + }; + ++#ifdef CONFIG_DRM_PANIC ++ + /** + * drm_panic_trylock - try to enter the panic printing critical section + * @dev: struct drm_device +@@ -149,4 +151,16 @@ struct drm_scanout_buffer { + #define drm_panic_unlock(dev, flags) \ + raw_spin_unlock_irqrestore(&(dev)->mode_config.panic_lock, flags) + ++#else ++ ++static inline bool drm_panic_trylock(struct drm_device *dev, unsigned long flags) ++{ ++ return true; ++} ++ ++static inline void drm_panic_lock(struct drm_device *dev, unsigned long flags) {} ++static inline void drm_panic_unlock(struct drm_device *dev, unsigned long flags) {} ++ ++#endif ++ + #endif /* __DRM_PANIC_H__ */ +-- +2.47.1 + diff --git a/queue-6.12/drm-sti-avoid-potential-dereference-of-error-pointers-in-sti_gdp_atomic_check.patch b/queue-6.12/drm-sti-avoid-potential-dereference-of-error-pointers-in-sti_gdp_atomic_check.patch new file mode 100644 index 00000000000..8242d994b89 --- /dev/null +++ b/queue-6.12/drm-sti-avoid-potential-dereference-of-error-pointers-in-sti_gdp_atomic_check.patch @@ -0,0 +1,36 @@ +From e965e771b069421c233d674c3c8cd8c7f7245f42 Mon Sep 17 00:00:00 2001 +From: Ma Ke +Date: Mon, 9 Sep 2024 14:33:59 +0800 +Subject: drm/sti: avoid potential dereference of error pointers in sti_gdp_atomic_check + +From: Ma Ke + +commit e965e771b069421c233d674c3c8cd8c7f7245f42 upstream. + +The return value of drm_atomic_get_crtc_state() needs to be +checked. To avoid use of error pointer 'crtc_state' in case +of the failure. + +Cc: stable@vger.kernel.org +Fixes: dd86dc2f9ae1 ("drm/sti: implement atomic_check for the planes") +Signed-off-by: Ma Ke +Acked-by: Alain Volmat +Link: https://patchwork.freedesktop.org/patch/msgid/20240909063359.1197065-1-make24@iscas.ac.cn +Signed-off-by: Alain Volmat +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/sti/sti_gdp.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/gpu/drm/sti/sti_gdp.c ++++ b/drivers/gpu/drm/sti/sti_gdp.c +@@ -638,6 +638,9 @@ static int sti_gdp_atomic_check(struct d + + mixer = to_sti_mixer(crtc); + crtc_state = drm_atomic_get_crtc_state(state, crtc); ++ if (IS_ERR(crtc_state)) ++ return PTR_ERR(crtc_state); ++ + mode = &crtc_state->mode; + dst_x = new_plane_state->crtc_x; + dst_y = new_plane_state->crtc_y; diff --git a/queue-6.12/drm-sti-avoid-potential-dereference-of-error-pointers-in-sti_hqvdp_atomic_check.patch b/queue-6.12/drm-sti-avoid-potential-dereference-of-error-pointers-in-sti_hqvdp_atomic_check.patch new file mode 100644 index 00000000000..17748f128af --- /dev/null +++ b/queue-6.12/drm-sti-avoid-potential-dereference-of-error-pointers-in-sti_hqvdp_atomic_check.patch @@ -0,0 +1,35 @@ +From c1ab40a1fdfee732c7e6ff2fb8253760293e47e8 Mon Sep 17 00:00:00 2001 +From: Ma Ke +Date: Fri, 13 Sep 2024 17:09:26 +0800 +Subject: drm/sti: avoid potential dereference of error pointers in sti_hqvdp_atomic_check + +From: Ma Ke + +commit c1ab40a1fdfee732c7e6ff2fb8253760293e47e8 upstream. + +The return value of drm_atomic_get_crtc_state() needs to be +checked. To avoid use of error pointer 'crtc_state' in case +of the failure. + +Cc: stable@vger.kernel.org +Fixes: dd86dc2f9ae1 ("drm/sti: implement atomic_check for the planes") +Signed-off-by: Ma Ke +Link: https://patchwork.freedesktop.org/patch/msgid/20240913090926.2023716-1-make24@iscas.ac.cn +Signed-off-by: Alain Volmat +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/sti/sti_hqvdp.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/gpu/drm/sti/sti_hqvdp.c ++++ b/drivers/gpu/drm/sti/sti_hqvdp.c +@@ -1037,6 +1037,9 @@ static int sti_hqvdp_atomic_check(struct + return 0; + + crtc_state = drm_atomic_get_crtc_state(state, crtc); ++ if (IS_ERR(crtc_state)) ++ return PTR_ERR(crtc_state); ++ + mode = &crtc_state->mode; + dst_x = new_plane_state->crtc_x; + dst_y = new_plane_state->crtc_y; diff --git a/queue-6.12/drm-sti-avoid-potential-dereference-of-error-pointers.patch b/queue-6.12/drm-sti-avoid-potential-dereference-of-error-pointers.patch new file mode 100644 index 00000000000..ab3840c6d8d --- /dev/null +++ b/queue-6.12/drm-sti-avoid-potential-dereference-of-error-pointers.patch @@ -0,0 +1,35 @@ +From 831214f77037de02afc287eae93ce97f218d8c04 Mon Sep 17 00:00:00 2001 +From: Ma Ke +Date: Fri, 13 Sep 2024 17:04:12 +0800 +Subject: drm/sti: avoid potential dereference of error pointers + +From: Ma Ke + +commit 831214f77037de02afc287eae93ce97f218d8c04 upstream. + +The return value of drm_atomic_get_crtc_state() needs to be +checked. To avoid use of error pointer 'crtc_state' in case +of the failure. + +Cc: stable@vger.kernel.org +Fixes: dd86dc2f9ae1 ("drm/sti: implement atomic_check for the planes") +Signed-off-by: Ma Ke +Link: https://patchwork.freedesktop.org/patch/msgid/20240913090412.2022848-1-make24@iscas.ac.cn +Signed-off-by: Alain Volmat +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/sti/sti_cursor.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/gpu/drm/sti/sti_cursor.c ++++ b/drivers/gpu/drm/sti/sti_cursor.c +@@ -200,6 +200,9 @@ static int sti_cursor_atomic_check(struc + return 0; + + crtc_state = drm_atomic_get_crtc_state(state, crtc); ++ if (IS_ERR(crtc_state)) ++ return PTR_ERR(crtc_state); ++ + mode = &crtc_state->mode; + dst_x = new_plane_state->crtc_x; + dst_y = new_plane_state->crtc_y; diff --git a/queue-6.12/drm-xe-guc_submit-fix-race-around-suspend_pending.patch b/queue-6.12/drm-xe-guc_submit-fix-race-around-suspend_pending.patch new file mode 100644 index 00000000000..8d013f6710a --- /dev/null +++ b/queue-6.12/drm-xe-guc_submit-fix-race-around-suspend_pending.patch @@ -0,0 +1,92 @@ +From 87651f31ae4e6e6e7e6c7270b9b469405e747407 Mon Sep 17 00:00:00 2001 +From: Matthew Auld +Date: Fri, 22 Nov 2024 16:19:17 +0000 +Subject: drm/xe/guc_submit: fix race around suspend_pending +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Matthew Auld + +commit 87651f31ae4e6e6e7e6c7270b9b469405e747407 upstream. + +Currently in some testcases we can trigger: + +xe 0000:03:00.0: [drm] Assertion `exec_queue_destroyed(q)` failed! +.... +WARNING: CPU: 18 PID: 2640 at drivers/gpu/drm/xe/xe_guc_submit.c:1826 xe_guc_sched_done_handler+0xa54/0xef0 [xe] +xe 0000:03:00.0: [drm] *ERROR* GT1: DEREGISTER_DONE: Unexpected engine state 0x00a1, guc_id=57 + +Looking at a snippet of corresponding ftrace for this GuC id we can see: + +162.673311: xe_sched_msg_add: dev=0000:03:00.0, gt=1 guc_id=57, opcode=3 +162.673317: xe_sched_msg_recv: dev=0000:03:00.0, gt=1 guc_id=57, opcode=3 +162.673319: xe_exec_queue_scheduling_disable: dev=0000:03:00.0, 1:0x2, gt=1, width=1, guc_id=57, guc_state=0x29, flags=0x0 +162.674089: xe_exec_queue_kill: dev=0000:03:00.0, 1:0x2, gt=1, width=1, guc_id=57, guc_state=0x29, flags=0x0 +162.674108: xe_exec_queue_close: dev=0000:03:00.0, 1:0x2, gt=1, width=1, guc_id=57, guc_state=0xa9, flags=0x0 +162.674488: xe_exec_queue_scheduling_done: dev=0000:03:00.0, 1:0x2, gt=1, width=1, guc_id=57, guc_state=0xa9, flags=0x0 +162.678452: xe_exec_queue_deregister: dev=0000:03:00.0, 1:0x2, gt=1, width=1, guc_id=57, guc_state=0xa1, flags=0x0 + +It looks like we try to suspend the queue (opcode=3), setting +suspend_pending and triggering a disable_scheduling. The user then +closes the queue. However the close will also forcefully signal the +suspend fence after killing the queue, later when the G2H response for +disable_scheduling comes back we have now cleared suspend_pending when +signalling the suspend fence, so the disable_scheduling now incorrectly +tries to also deregister the queue. This leads to warnings since the queue +has yet to even be marked for destruction. We also seem to trigger +errors later with trying to double unregister the same queue. + +To fix this tweak the ordering when handling the response to ensure we +don't race with a disable_scheduling that didn't actually intend to +perform an unregister. The destruction path should now also correctly +wait for any pending_disable before marking as destroyed. + +Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs") +Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/3371 +Signed-off-by: Matthew Auld +Cc: Matthew Brost +Cc: # v6.8+ +Reviewed-by: Matthew Brost +Link: https://patchwork.freedesktop.org/patch/msgid/20241122161914.321263-6-matthew.auld@intel.com +(cherry picked from commit f161809b362f027b6d72bd998e47f8f0bad60a2e) +Signed-off-by: Thomas Hellström +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/xe/xe_guc_submit.c | 17 +++++++++++++++-- + 1 file changed, 15 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/xe/xe_guc_submit.c ++++ b/drivers/gpu/drm/xe/xe_guc_submit.c +@@ -1846,16 +1846,29 @@ static void handle_sched_done(struct xe_ + xe_gt_assert(guc_to_gt(guc), runnable_state == 0); + xe_gt_assert(guc_to_gt(guc), exec_queue_pending_disable(q)); + +- clear_exec_queue_pending_disable(q); + if (q->guc->suspend_pending) { + suspend_fence_signal(q); ++ clear_exec_queue_pending_disable(q); + } else { + if (exec_queue_banned(q) || check_timeout) { + smp_wmb(); + wake_up_all(&guc->ct.wq); + } +- if (!check_timeout) ++ if (!check_timeout && exec_queue_destroyed(q)) { ++ /* ++ * Make sure to clear the pending_disable only ++ * after sampling the destroyed state. We want ++ * to ensure we don't trigger the unregister too ++ * early with something intending to only ++ * disable scheduling. The caller doing the ++ * destroy must wait for an ongoing ++ * pending_disable before marking as destroyed. ++ */ ++ clear_exec_queue_pending_disable(q); + deregister_exec_queue(guc, q); ++ } else { ++ clear_exec_queue_pending_disable(q); ++ } + } + } + } diff --git a/queue-6.12/drm-xe-migrate-fix-pat-index-usage.patch b/queue-6.12/drm-xe-migrate-fix-pat-index-usage.patch new file mode 100644 index 00000000000..ae2ae9df73b --- /dev/null +++ b/queue-6.12/drm-xe-migrate-fix-pat-index-usage.patch @@ -0,0 +1,55 @@ +From 23346f85163de83aca6dc30dde3944131cf54706 Mon Sep 17 00:00:00 2001 +From: Matthew Auld +Date: Tue, 26 Nov 2024 18:13:00 +0000 +Subject: drm/xe/migrate: fix pat index usage +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Matthew Auld + +commit 23346f85163de83aca6dc30dde3944131cf54706 upstream. + +XE_CACHE_WB must be converted into the per-platform pat index for that +particular caching mode, otherwise we are just encoding whatever happens +to be the value of that enum. + +Fixes: e8babb280b5e ("drm/xe: Convert multiple bind ops into single job") +Signed-off-by: Matthew Auld +Cc: Matthew Brost +Cc: Nirmoy Das +Cc: # v6.12+ +Reviewed-by: Nirmoy Das +Reviewed-by: Matthew Brost +Link: https://patchwork.freedesktop.org/patch/msgid/20241126181259.159713-3-matthew.auld@intel.com +(cherry picked from commit f3dc9246f9c3cd5a7d8fd70cfd805bfc52214e2e) +Signed-off-by: Thomas Hellström +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/xe/xe_migrate.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c +index cfd31ae49cc1..48e205a40fd2 100644 +--- a/drivers/gpu/drm/xe/xe_migrate.c ++++ b/drivers/gpu/drm/xe/xe_migrate.c +@@ -1350,6 +1350,7 @@ __xe_migrate_update_pgtables(struct xe_migrate *m, + + /* For sysmem PTE's, need to map them in our hole.. */ + if (!IS_DGFX(xe)) { ++ u16 pat_index = xe->pat.idx[XE_CACHE_WB]; + u32 ptes, ofs; + + ppgtt_ofs = NUM_KERNEL_PDE - 1; +@@ -1409,7 +1410,7 @@ __xe_migrate_update_pgtables(struct xe_migrate *m, + pt_bo->update_index = current_update; + + addr = vm->pt_ops->pte_encode_bo(pt_bo, 0, +- XE_CACHE_WB, 0); ++ pat_index, 0); + bb->cs[bb->len++] = lower_32_bits(addr); + bb->cs[bb->len++] = upper_32_bits(addr); + } +-- +2.47.1 + diff --git a/queue-6.12/drm-xe-migrate-use-xe_bo_flag_pagetable.patch b/queue-6.12/drm-xe-migrate-use-xe_bo_flag_pagetable.patch new file mode 100644 index 00000000000..ab54d640b25 --- /dev/null +++ b/queue-6.12/drm-xe-migrate-use-xe_bo_flag_pagetable.patch @@ -0,0 +1,45 @@ +From c78f4399188369a55eed69cbf19a8aad2a65ac75 Mon Sep 17 00:00:00 2001 +From: Matthew Auld +Date: Tue, 26 Nov 2024 18:13:01 +0000 +Subject: drm/xe/migrate: use XE_BO_FLAG_PAGETABLE +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Matthew Auld + +commit c78f4399188369a55eed69cbf19a8aad2a65ac75 upstream. + +On some HW we want to avoid the host caching PTEs, since access from GPU +side can be incoherent. However here the special migrate object is +mapping PTEs which are written from the host and potentially cached. Use +XE_BO_FLAG_PAGETABLE to ensure that non-cached mapping is used, on +platforms where this matters. + +Fixes: 7a060d786cc1 ("drm/xe/mtl: Map PPGTT as CPU:WC") +Signed-off-by: Matthew Auld +Cc: Matthew Brost +Cc: Nirmoy Das +Cc: # v6.8+ +Reviewed-by: Nirmoy Das +Reviewed-by: Matthew Brost +Link: https://patchwork.freedesktop.org/patch/msgid/20241126181259.159713-4-matthew.auld@intel.com +(cherry picked from commit febc689b27d28973cd02f667548a5dca383d859a) +Signed-off-by: Thomas Hellström +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/xe/xe_migrate.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/xe/xe_migrate.c ++++ b/drivers/gpu/drm/xe/xe_migrate.c +@@ -209,7 +209,8 @@ static int xe_migrate_prepare_vm(struct + num_entries * XE_PAGE_SIZE, + ttm_bo_type_kernel, + XE_BO_FLAG_VRAM_IF_DGFX(tile) | +- XE_BO_FLAG_PINNED); ++ XE_BO_FLAG_PINNED | ++ XE_BO_FLAG_PAGETABLE); + if (IS_ERR(bo)) + return PTR_ERR(bo); + diff --git a/queue-6.12/drm-xe-xe_guc_ads-save-restore-oa-registers-and-allowlist-regs.patch b/queue-6.12/drm-xe-xe_guc_ads-save-restore-oa-registers-and-allowlist-regs.patch new file mode 100644 index 00000000000..fbbc831e198 --- /dev/null +++ b/queue-6.12/drm-xe-xe_guc_ads-save-restore-oa-registers-and-allowlist-regs.patch @@ -0,0 +1,72 @@ +From 55858fa7eb2f163f7aa34339fd3399ba4ff564c6 Mon Sep 17 00:00:00 2001 +From: Jonathan Cavitt +Date: Wed, 23 Oct 2024 20:07:15 +0000 +Subject: drm/xe/xe_guc_ads: save/restore OA registers and allowlist regs + +From: Jonathan Cavitt + +commit 55858fa7eb2f163f7aa34339fd3399ba4ff564c6 upstream. + +Several OA registers and allowlist registers were missing from the +save/restore list for GuC and could be lost during an engine reset. Add +them to the list. + +v2: +- Fix commit message (Umesh) +- Add missing closes (Ashutosh) + +v3: +- Add missing fixes (Ashutosh) + +Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/2249 +Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs") +Suggested-by: Umesh Nerlige Ramappa +Suggested-by: John Harrison +Signed-off-by: Jonathan Cavitt +CC: stable@vger.kernel.org # v6.11+ +Reviewed-by: Umesh Nerlige Ramappa +Reviewed-by: Ashutosh Dixit +Signed-off-by: Ashutosh Dixit +Link: https://patchwork.freedesktop.org/patch/msgid/20241023200716.82624-1-jonathan.cavitt@intel.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/xe/xe_guc_ads.c | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +--- a/drivers/gpu/drm/xe/xe_guc_ads.c ++++ b/drivers/gpu/drm/xe/xe_guc_ads.c +@@ -13,6 +13,7 @@ + #include "regs/xe_engine_regs.h" + #include "regs/xe_gt_regs.h" + #include "regs/xe_guc_regs.h" ++#include "regs/xe_oa_regs.h" + #include "xe_bo.h" + #include "xe_gt.h" + #include "xe_gt_ccs_mode.h" +@@ -601,6 +602,11 @@ static unsigned int guc_mmio_regset_writ + guc_mmio_regset_write_one(ads, regset_map, e->reg, count++); + } + ++ for (i = 0; i < RING_MAX_NONPRIV_SLOTS; i++) ++ guc_mmio_regset_write_one(ads, regset_map, ++ RING_FORCE_TO_NONPRIV(hwe->mmio_base, i), ++ count++); ++ + /* Wa_1607983814 */ + if (needs_wa_1607983814(xe) && hwe->class == XE_ENGINE_CLASS_RENDER) { + for (i = 0; i < LNCFCMOCS_REG_COUNT; i++) { +@@ -609,6 +615,14 @@ static unsigned int guc_mmio_regset_writ + } + } + ++ guc_mmio_regset_write_one(ads, regset_map, EU_PERF_CNTL0, count++); ++ guc_mmio_regset_write_one(ads, regset_map, EU_PERF_CNTL1, count++); ++ guc_mmio_regset_write_one(ads, regset_map, EU_PERF_CNTL2, count++); ++ guc_mmio_regset_write_one(ads, regset_map, EU_PERF_CNTL3, count++); ++ guc_mmio_regset_write_one(ads, regset_map, EU_PERF_CNTL4, count++); ++ guc_mmio_regset_write_one(ads, regset_map, EU_PERF_CNTL5, count++); ++ guc_mmio_regset_write_one(ads, regset_map, EU_PERF_CNTL6, count++); ++ + return count; + } + diff --git a/queue-6.12/drm-xlnx-zynqmp_dpsub-fix-hotplug-detection.patch b/queue-6.12/drm-xlnx-zynqmp_dpsub-fix-hotplug-detection.patch new file mode 100644 index 00000000000..7b34e1951e3 --- /dev/null +++ b/queue-6.12/drm-xlnx-zynqmp_dpsub-fix-hotplug-detection.patch @@ -0,0 +1,40 @@ +From 71ba1c9b1c717831920c3d432404ee5a707e04b4 Mon Sep 17 00:00:00 2001 +From: Steffen Dirkwinkel +Date: Mon, 28 Oct 2024 14:42:17 +0100 +Subject: drm: xlnx: zynqmp_dpsub: fix hotplug detection + +From: Steffen Dirkwinkel + +commit 71ba1c9b1c717831920c3d432404ee5a707e04b4 upstream. + +drm_kms_helper_poll_init needs to be called after zynqmp_dpsub_kms_init. +zynqmp_dpsub_kms_init creates the connector and without it we don't +enable hotplug detection. + +Fixes: eb2d64bfcc17 ("drm: xlnx: zynqmp_dpsub: Report HPD through the bridge") +Cc: stable@vger.kernel.org +Signed-off-by: Steffen Dirkwinkel +Signed-off-by: Tomi Valkeinen +Link: https://patchwork.freedesktop.org/patch/msgid/20241028134218.54727-1-lists@steffen.cc +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/xlnx/zynqmp_kms.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/xlnx/zynqmp_kms.c ++++ b/drivers/gpu/drm/xlnx/zynqmp_kms.c +@@ -509,12 +509,12 @@ int zynqmp_dpsub_drm_init(struct zynqmp_ + if (ret) + return ret; + +- drm_kms_helper_poll_init(drm); +- + ret = zynqmp_dpsub_kms_init(dpsub); + if (ret < 0) + goto err_poll_fini; + ++ drm_kms_helper_poll_init(drm); ++ + /* Reset all components and register the DRM device. */ + drm_mode_config_reset(drm); + diff --git a/queue-6.12/revert-drm-radeon-delay-connector-detecting-when-hpd-singals-is-unstable.patch b/queue-6.12/revert-drm-radeon-delay-connector-detecting-when-hpd-singals-is-unstable.patch new file mode 100644 index 00000000000..abad77a638d --- /dev/null +++ b/queue-6.12/revert-drm-radeon-delay-connector-detecting-when-hpd-singals-is-unstable.patch @@ -0,0 +1,46 @@ +From 979bfe291b5b30a9132c2fd433247e677b24c6aa Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Thu, 14 Nov 2024 16:23:45 -0500 +Subject: Revert "drm/radeon: Delay Connector detecting when HPD singals is unstable" + +From: Alex Deucher + +commit 979bfe291b5b30a9132c2fd433247e677b24c6aa upstream. + +This reverts commit 949658cb9b69ab9d22a42a662b2fdc7085689ed8. + +This causes a blank screen on boot. + +Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3696 +Signed-off-by: Alex Deucher +Cc: Shixiong Ou +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/radeon/radeon_connectors.c | 10 ---------- + 1 file changed, 10 deletions(-) + +diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c +index f9c73c55f04f..f9996304d943 100644 +--- a/drivers/gpu/drm/radeon/radeon_connectors.c ++++ b/drivers/gpu/drm/radeon/radeon_connectors.c +@@ -1255,16 +1255,6 @@ radeon_dvi_detect(struct drm_connector *connector, bool force) + goto exit; + } + } +- +- if (dret && radeon_connector->hpd.hpd != RADEON_HPD_NONE && +- !radeon_hpd_sense(rdev, radeon_connector->hpd.hpd) && +- connector->connector_type == DRM_MODE_CONNECTOR_HDMIA) { +- DRM_DEBUG_KMS("EDID is readable when HPD disconnected\n"); +- schedule_delayed_work(&rdev->hotplug_work, msecs_to_jiffies(1000)); +- ret = connector_status_disconnected; +- goto exit; +- } +- + if (dret) { + radeon_connector->detected_by_load = false; + radeon_connector_free_edid(connector); +-- +2.47.1 + diff --git a/queue-6.12/series b/queue-6.12/series index 4afb01bdcf0..55ad6900b32 100644 --- a/queue-6.12/series +++ b/queue-6.12/series @@ -116,3 +116,30 @@ binder-add-delivered_freeze-to-debugfs-output.patch dt-bindings-net-fec-add-pps-channel-property.patch net-fec-refactor-pps-channel-configuration.patch net-fec-make-pps-channel-configurable.patch +drm-panic-fix-uninitialized-spinlock-acquisition-with-config_drm_panic-n.patch +drm-sti-avoid-potential-dereference-of-error-pointers-in-sti_hqvdp_atomic_check.patch +drm-sti-avoid-potential-dereference-of-error-pointers-in-sti_gdp_atomic_check.patch +drm-panel-jd9365da-h3-remove-unused-num_init_cmds-structure-member.patch +drm-sti-avoid-potential-dereference-of-error-pointers.patch +drm-fbdev-dma-select-fb_deferred_io.patch +drm-mediatek-fix-child-node-refcount-handling-in-early-exit.patch +drm-bridge-it6505-fix-inverted-reset-polarity.patch +drm-etnaviv-flush-shader-l1-cache-after-user-commandstream.patch +drm-xlnx-zynqmp_dpsub-fix-hotplug-detection.patch +drm-xe-xe_guc_ads-save-restore-oa-registers-and-allowlist-regs.patch +drm-xe-migrate-fix-pat-index-usage.patch +revert-drm-radeon-delay-connector-detecting-when-hpd-singals-is-unstable.patch +drm-xe-migrate-use-xe_bo_flag_pagetable.patch +drm-xe-guc_submit-fix-race-around-suspend_pending.patch +drm-amdkfd-use-the-correct-wptr-size.patch +drm-amdgpu-pm-add-gen5-display-to-the-user-on-smu-v14.0.2-3.patch +drm-amd-add-some-missing-straps-from-nbio-7.11.0.patch +drm-amdgpu-fix-usage-slab-after-free.patch +drm-amd-pm-skip-setting-the-power-source-on-smu-v14.0.2-3.patch +drm-amd-fix-initialization-mistake-for-nbio-7.11-devices.patch +drm-amd-pm-update-current_socclk-and-current_uclk-in-gpu_metrics-on-smu-v13.0.7.patch +drm-amd-pm-disable-pcie-speed-switching-on-intel-platform-for-smu-v14.0.2-3.patch +drm-amd-pm-remove-arcturus-min-power-limit.patch +drm-amd-display-fix-handling-of-plane-refcount.patch +drm-amd-display-update-pipe-selection-policy-to-check-head-pipe.patch +drm-amd-display-remove-pipe_dto_src_sel-programming-from-set_dtbclk_dto.patch