From: Greg Kroah-Hartman Date: Fri, 29 Mar 2024 13:19:05 +0000 (+0100) Subject: 6.7-stable patches X-Git-Tag: v6.7.12~139 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=493f99b3da3ff4ed6c0329d1d71abd499e36676a;p=thirdparty%2Fkernel%2Fstable-queue.git 6.7-stable patches added patches: drm-i915-include-the-pll-name-in-the-debug-messages.patch drm-i915-replace-a-memset-with-zero-initialization.patch drm-i915-stop-printing-pipe-name-as-hex.patch drm-i915-suppress-old-pll-pipe_mask-checks-for-mg-tc-tbt-plls.patch drm-i915-try-to-preserve-the-current-shared_dpll-for-fastset-on-type-c-ports.patch drm-i915-use-named-initializers-for-dpll-info.patch perf-top-use-evsel-s-cpus-to-replace-user_requested_cpus.patch --- diff --git a/queue-6.7/drm-i915-include-the-pll-name-in-the-debug-messages.patch b/queue-6.7/drm-i915-include-the-pll-name-in-the-debug-messages.patch new file mode 100644 index 00000000000..5eb74e9a09f --- /dev/null +++ b/queue-6.7/drm-i915-include-the-pll-name-in-the-debug-messages.patch @@ -0,0 +1,105 @@ +From d283ee5662c6bf2f3771a36b926f6988e6dddfc6 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= +Date: Tue, 23 Jan 2024 11:31:35 +0200 +Subject: drm/i915: Include the PLL name in the debug messages +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ville Syrjälä + +commit d283ee5662c6bf2f3771a36b926f6988e6dddfc6 upstream. + +Make the log easier to parse by including the name of the PLL +in the debug prints regarding said PLL. + +Signed-off-by: Ville Syrjälä +Link: https://patchwork.freedesktop.org/patch/msgid/20240123093137.9133-1-ville.syrjala@linux.intel.com +Reviewed-by: Jani Nikula +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 39 +++++++++++++------------- + 1 file changed, 20 insertions(+), 19 deletions(-) + +--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c ++++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +@@ -4476,25 +4476,25 @@ verify_single_dpll_state(struct drm_i915 + u8 pipe_mask; + bool active; + +- drm_dbg_kms(&i915->drm, "%s\n", pll->info->name); +- + active = intel_dpll_get_hw_state(i915, pll, &dpll_hw_state); + + if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) { + I915_STATE_WARN(i915, !pll->on && pll->active_mask, +- "pll in active use but not on in sw tracking\n"); ++ "%s: pll in active use but not on in sw tracking\n", ++ pll->info->name); + I915_STATE_WARN(i915, pll->on && !pll->active_mask, +- "pll is on but not used by any active pipe\n"); ++ "%s: pll is on but not used by any active pipe\n", ++ pll->info->name); + I915_STATE_WARN(i915, pll->on != active, +- "pll on state mismatch (expected %i, found %i)\n", +- pll->on, active); ++ "%s: pll on state mismatch (expected %i, found %i)\n", ++ pll->info->name, pll->on, active); + } + + if (!crtc) { + I915_STATE_WARN(i915, + pll->active_mask & ~pll->state.pipe_mask, +- "more active pll users than references: 0x%x vs 0x%x\n", +- pll->active_mask, pll->state.pipe_mask); ++ "%s: more active pll users than references: 0x%x vs 0x%x\n", ++ pll->info->name, pll->active_mask, pll->state.pipe_mask); + + return; + } +@@ -4503,21 +4503,22 @@ verify_single_dpll_state(struct drm_i915 + + if (new_crtc_state->hw.active) + I915_STATE_WARN(i915, !(pll->active_mask & pipe_mask), +- "pll active mismatch (expected pipe %c in active mask 0x%x)\n", +- pipe_name(crtc->pipe), pll->active_mask); ++ "%s: pll active mismatch (expected pipe %c in active mask 0x%x)\n", ++ pll->info->name, pipe_name(crtc->pipe), pll->active_mask); + else + I915_STATE_WARN(i915, pll->active_mask & pipe_mask, +- "pll active mismatch (didn't expect pipe %c in active mask 0x%x)\n", +- pipe_name(crtc->pipe), pll->active_mask); ++ "%s: pll active mismatch (didn't expect pipe %c in active mask 0x%x)\n", ++ pll->info->name, pipe_name(crtc->pipe), pll->active_mask); + + I915_STATE_WARN(i915, !(pll->state.pipe_mask & pipe_mask), +- "pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n", +- pipe_mask, pll->state.pipe_mask); ++ "%s: pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n", ++ pll->info->name, pipe_mask, pll->state.pipe_mask); + + I915_STATE_WARN(i915, + pll->on && memcmp(&pll->state.hw_state, &dpll_hw_state, + sizeof(dpll_hw_state)), +- "pll hw state mismatch\n"); ++ "%s: pll hw state mismatch\n", ++ pll->info->name); + } + + void intel_shared_dpll_state_verify(struct intel_atomic_state *state, +@@ -4539,11 +4540,11 @@ void intel_shared_dpll_state_verify(stru + struct intel_shared_dpll *pll = old_crtc_state->shared_dpll; + + I915_STATE_WARN(i915, pll->active_mask & pipe_mask, +- "pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n", +- pipe_name(crtc->pipe), pll->active_mask); ++ "%s: pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n", ++ pll->info->name, pipe_name(crtc->pipe), pll->active_mask); + I915_STATE_WARN(i915, pll->state.pipe_mask & pipe_mask, +- "pll enabled crtcs mismatch (found pipe %c in enabled mask (0x%x))\n", +- pipe_name(crtc->pipe), pll->state.pipe_mask); ++ "%s: pll enabled crtcs mismatch (found pipe %c in enabled mask (0x%x))\n", ++ pll->info->name, pipe_name(crtc->pipe), pll->state.pipe_mask); + } + } + diff --git a/queue-6.7/drm-i915-replace-a-memset-with-zero-initialization.patch b/queue-6.7/drm-i915-replace-a-memset-with-zero-initialization.patch new file mode 100644 index 00000000000..9ea533392fc --- /dev/null +++ b/queue-6.7/drm-i915-replace-a-memset-with-zero-initialization.patch @@ -0,0 +1,40 @@ +From 92b47c3b8b242a1f1b73d5c1181d5b678ac1382b Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= +Date: Fri, 24 Nov 2023 10:27:32 +0200 +Subject: drm/i915: Replace a memset() with zero initialization +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ville Syrjälä + +commit 92b47c3b8b242a1f1b73d5c1181d5b678ac1382b upstream. + +Declaring a struct and immediately zeroing it with memset() +seems a bit silly to me. Just zero initialize the struct +when declaring it. + +Signed-off-by: Ville Syrjälä +Link: https://patchwork.freedesktop.org/patch/msgid/20231124082735.25470-2-ville.syrjala@linux.intel.com +Reviewed-by: Mika Kahola +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 4 +--- + 1 file changed, 1 insertion(+), 3 deletions(-) + +--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c ++++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +@@ -4466,12 +4466,10 @@ verify_single_dpll_state(struct drm_i915 + struct intel_crtc *crtc, + const struct intel_crtc_state *new_crtc_state) + { +- struct intel_dpll_hw_state dpll_hw_state; ++ struct intel_dpll_hw_state dpll_hw_state = {}; + u8 pipe_mask; + bool active; + +- memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); +- + drm_dbg_kms(&i915->drm, "%s\n", pll->info->name); + + active = intel_dpll_get_hw_state(i915, pll, &dpll_hw_state); diff --git a/queue-6.7/drm-i915-stop-printing-pipe-name-as-hex.patch b/queue-6.7/drm-i915-stop-printing-pipe-name-as-hex.patch new file mode 100644 index 00000000000..d4c55117c0f --- /dev/null +++ b/queue-6.7/drm-i915-stop-printing-pipe-name-as-hex.patch @@ -0,0 +1,33 @@ +From 58046e6cf811464b8a6f269dc6a40a8cb91a8a68 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= +Date: Wed, 22 Nov 2023 11:31:36 +0200 +Subject: drm/i915: Stop printing pipe name as hex +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ville Syrjälä + +commit 58046e6cf811464b8a6f269dc6a40a8cb91a8a68 upstream. + +Print the pipe name in ascii rather than hex. + +Signed-off-by: Ville Syrjälä +Link: https://patchwork.freedesktop.org/patch/msgid/20231122093137.1509-3-ville.syrjala@linux.intel.com +Reviewed-by: Jouni Högander +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c ++++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +@@ -4534,7 +4534,7 @@ void intel_shared_dpll_state_verify(stru + "pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n", + pipe_name(crtc->pipe), pll->active_mask); + I915_STATE_WARN(i915, pll->state.pipe_mask & pipe_mask, +- "pll enabled crtcs mismatch (found %x in enabled mask (0x%x))\n", ++ "pll enabled crtcs mismatch (found pipe %c in enabled mask (0x%x))\n", + pipe_name(crtc->pipe), pll->state.pipe_mask); + } + } diff --git a/queue-6.7/drm-i915-suppress-old-pll-pipe_mask-checks-for-mg-tc-tbt-plls.patch b/queue-6.7/drm-i915-suppress-old-pll-pipe_mask-checks-for-mg-tc-tbt-plls.patch new file mode 100644 index 00000000000..34ca78a7bcb --- /dev/null +++ b/queue-6.7/drm-i915-suppress-old-pll-pipe_mask-checks-for-mg-tc-tbt-plls.patch @@ -0,0 +1,111 @@ +From 33c7760226c79ee8de6c0646640963a8a7ee794a Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= +Date: Tue, 23 Jan 2024 11:31:36 +0200 +Subject: drm/i915: Suppress old PLL pipe_mask checks for MG/TC/TBT PLLs +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ville Syrjälä + +commit 33c7760226c79ee8de6c0646640963a8a7ee794a upstream. + +TC ports have both the MG/TC and TBT PLLs selected simultanously (so +that we can switch from MG/TC to TBT as a fallback). This doesn't play +well with the state checker that assumes that the old PLL shouldn't +have the pipe in its pipe_mask anymore. Suppress that check for these +PLLs to avoid spurious WARNs when you disconnect a TC port and a +non-disabling modeset happens before actually disabling the port. + +v2: Only suppress when one of the PLLs is the TBT PLL and the + other one is not + +Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9816 +Signed-off-by: Ville Syrjälä +Link: https://patchwork.freedesktop.org/patch/msgid/20240123093137.9133-2-ville.syrjala@linux.intel.com +Reviewed-by: Jani Nikula +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 23 +++++++++++++++++++---- + drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 4 ++++ + 2 files changed, 23 insertions(+), 4 deletions(-) + +--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c ++++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +@@ -4026,7 +4026,8 @@ static const struct intel_shared_dpll_fu + static const struct dpll_info icl_plls[] = { + { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, }, + { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, }, +- { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, }, ++ { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, ++ .flags = INTEL_DPLL_IS_ALT_PORT_DPLL, }, + { .name = "MG PLL 1", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, }, + { .name = "MG PLL 2", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, }, + { .name = "MG PLL 3", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, }, +@@ -4070,7 +4071,8 @@ static const struct intel_shared_dpll_fu + static const struct dpll_info tgl_plls[] = { + { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, }, + { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, }, +- { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, }, ++ { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, ++ .flags = INTEL_DPLL_IS_ALT_PORT_DPLL, }, + { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, }, + { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, }, + { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, }, +@@ -4143,7 +4145,8 @@ static const struct intel_dpll_mgr adls_ + static const struct dpll_info adlp_plls[] = { + { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, }, + { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, }, +- { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, }, ++ { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, ++ .flags = INTEL_DPLL_IS_ALT_PORT_DPLL, }, + { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, }, + { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, }, + { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, }, +@@ -4521,6 +4524,14 @@ verify_single_dpll_state(struct drm_i915 + pll->info->name); + } + ++static bool has_alt_port_dpll(const struct intel_shared_dpll *old_pll, ++ const struct intel_shared_dpll *new_pll) ++{ ++ return old_pll && new_pll && old_pll != new_pll && ++ (old_pll->info->flags & INTEL_DPLL_IS_ALT_PORT_DPLL || ++ new_pll->info->flags & INTEL_DPLL_IS_ALT_PORT_DPLL); ++} ++ + void intel_shared_dpll_state_verify(struct intel_atomic_state *state, + struct intel_crtc *crtc) + { +@@ -4542,7 +4553,11 @@ void intel_shared_dpll_state_verify(stru + I915_STATE_WARN(i915, pll->active_mask & pipe_mask, + "%s: pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n", + pll->info->name, pipe_name(crtc->pipe), pll->active_mask); +- I915_STATE_WARN(i915, pll->state.pipe_mask & pipe_mask, ++ ++ /* TC ports have both MG/TC and TBT PLL referenced simultaneously */ ++ I915_STATE_WARN(i915, !has_alt_port_dpll(old_crtc_state->shared_dpll, ++ new_crtc_state->shared_dpll) && ++ pll->state.pipe_mask & pipe_mask, + "%s: pll enabled crtcs mismatch (found pipe %c in enabled mask (0x%x))\n", + pll->info->name, pipe_name(crtc->pipe), pll->state.pipe_mask); + } +--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h ++++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h +@@ -271,12 +271,16 @@ struct dpll_info { + enum intel_dpll_id id; + + #define INTEL_DPLL_ALWAYS_ON (1 << 0) ++#define INTEL_DPLL_IS_ALT_PORT_DPLL (1 << 1) + /** + * @flags: + * + * INTEL_DPLL_ALWAYS_ON + * Inform the state checker that the DPLL is kept enabled even if + * not in use by any CRTC. ++ * INTEL_DPLL_IS_ALT_PORT_DPLL ++ * Inform the state checker that the DPLL can be used as a fallback ++ * (for TC->TBT fallback). + */ + u32 flags; + }; diff --git a/queue-6.7/drm-i915-try-to-preserve-the-current-shared_dpll-for-fastset-on-type-c-ports.patch b/queue-6.7/drm-i915-try-to-preserve-the-current-shared_dpll-for-fastset-on-type-c-ports.patch new file mode 100644 index 00000000000..9023a78ac93 --- /dev/null +++ b/queue-6.7/drm-i915-try-to-preserve-the-current-shared_dpll-for-fastset-on-type-c-ports.patch @@ -0,0 +1,66 @@ +From ba407525f8247ee4c270369f3371b9994c27bfda Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= +Date: Thu, 18 Jan 2024 16:24:36 +0200 +Subject: drm/i915: Try to preserve the current shared_dpll for fastset on type-c ports +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ville Syrjälä + +commit ba407525f8247ee4c270369f3371b9994c27bfda upstream. + +Currently icl_compute_tc_phy_dplls() assumes that the active +PLL will be the TC PLL (as opposed to the TBT PLL). The actual +PLL will be selected during the modeset enable sequence, but +we need to put *something* into the crtc_state->shared_dpll +already during compute_config(). + +The downside of assuming one PLL or the other is that we'll +fail to fastset if the assumption doesn't match what was in +use previously. So let's instead keep the same PLL that was +in use previously (assuming there was one). This should allow +fastset to work again when using TBT PLL, at least in the +steady state. + +Now, assuming we want keep the same PLL may not be entirely +correct either. But we should be covered by the type-c link +reset handling which will force a full modeset by flagging +connectors_changed=true which means the resulting modeset +can't be converted into a fastset even if the full crtc state +looks identical. + +Cc: Imre Deak +Cc: Suraj Kandpal +Signed-off-by: Ville Syrjälä +Link: https://patchwork.freedesktop.org/patch/msgid/20240118142436.25928-1-ville.syrjala@linux.intel.com +Reviewed-by: Suraj Kandpal +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 8 +++++++- + 1 file changed, 7 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c ++++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +@@ -3288,6 +3288,8 @@ static int icl_compute_tc_phy_dplls(stru + struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_crtc_state *crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); ++ const struct intel_crtc_state *old_crtc_state = ++ intel_atomic_get_old_crtc_state(state, crtc); + struct icl_port_dpll *port_dpll = + &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; + struct skl_wrpll_params pll_params = {}; +@@ -3306,7 +3308,11 @@ static int icl_compute_tc_phy_dplls(stru + return ret; + + /* this is mainly for the fastset check */ +- icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY); ++ if (old_crtc_state->shared_dpll && ++ old_crtc_state->shared_dpll->info->id == DPLL_ID_ICL_TBTPLL) ++ icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT); ++ else ++ icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY); + + crtc_state->port_clock = icl_ddi_mg_pll_get_freq(i915, NULL, + &port_dpll->hw_state); diff --git a/queue-6.7/drm-i915-use-named-initializers-for-dpll-info.patch b/queue-6.7/drm-i915-use-named-initializers-for-dpll-info.patch new file mode 100644 index 00000000000..69146e82297 --- /dev/null +++ b/queue-6.7/drm-i915-use-named-initializers-for-dpll-info.patch @@ -0,0 +1,233 @@ +From f215038f4133ea9d1b525e9bb812527fe002db2b Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= +Date: Thu, 12 Oct 2023 15:35:19 +0300 +Subject: drm/i915: Use named initializers for DPLL info +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ville Syrjälä + +commit f215038f4133ea9d1b525e9bb812527fe002db2b upstream. + +Use named initializers when populating the DPLL info. This +is just more convenient and less error prone as we no longer +have to keep the initializers in a specific order. + +Signed-off-by: Ville Syrjälä +Link: https://patchwork.freedesktop.org/patch/msgid/20231012123522.26045-2-ville.syrjala@linux.intel.com +Reviewed-by: Jani Nikula +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 130 +++++++++++++------------- + 1 file changed, 67 insertions(+), 63 deletions(-) + +--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c ++++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +@@ -631,9 +631,9 @@ static const struct intel_shared_dpll_fu + }; + + static const struct dpll_info pch_plls[] = { +- { "PCH DPLL A", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_A, 0 }, +- { "PCH DPLL B", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_B, 0 }, +- { }, ++ { .name = "PCH DPLL A", .funcs = &ibx_pch_dpll_funcs, .id = DPLL_ID_PCH_PLL_A, }, ++ { .name = "PCH DPLL B", .funcs = &ibx_pch_dpll_funcs, .id = DPLL_ID_PCH_PLL_B, }, ++ {} + }; + + static const struct intel_dpll_mgr pch_pll_mgr = { +@@ -1239,13 +1239,16 @@ static const struct intel_shared_dpll_fu + }; + + static const struct dpll_info hsw_plls[] = { +- { "WRPLL 1", &hsw_ddi_wrpll_funcs, DPLL_ID_WRPLL1, 0 }, +- { "WRPLL 2", &hsw_ddi_wrpll_funcs, DPLL_ID_WRPLL2, 0 }, +- { "SPLL", &hsw_ddi_spll_funcs, DPLL_ID_SPLL, 0 }, +- { "LCPLL 810", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_810, INTEL_DPLL_ALWAYS_ON }, +- { "LCPLL 1350", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_1350, INTEL_DPLL_ALWAYS_ON }, +- { "LCPLL 2700", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_2700, INTEL_DPLL_ALWAYS_ON }, +- { }, ++ { .name = "WRPLL 1", .funcs = &hsw_ddi_wrpll_funcs, .id = DPLL_ID_WRPLL1, }, ++ { .name = "WRPLL 2", .funcs = &hsw_ddi_wrpll_funcs, .id = DPLL_ID_WRPLL2, }, ++ { .name = "SPLL", .funcs = &hsw_ddi_spll_funcs, .id = DPLL_ID_SPLL, }, ++ { .name = "LCPLL 810", .funcs = &hsw_ddi_lcpll_funcs, .id = DPLL_ID_LCPLL_810, ++ .flags = INTEL_DPLL_ALWAYS_ON, }, ++ { .name = "LCPLL 1350", .funcs = &hsw_ddi_lcpll_funcs, .id = DPLL_ID_LCPLL_1350, ++ .flags = INTEL_DPLL_ALWAYS_ON, }, ++ { .name = "LCPLL 2700", .funcs = &hsw_ddi_lcpll_funcs, .id = DPLL_ID_LCPLL_2700, ++ .flags = INTEL_DPLL_ALWAYS_ON, }, ++ {} + }; + + static const struct intel_dpll_mgr hsw_pll_mgr = { +@@ -1921,11 +1924,12 @@ static const struct intel_shared_dpll_fu + }; + + static const struct dpll_info skl_plls[] = { +- { "DPLL 0", &skl_ddi_dpll0_funcs, DPLL_ID_SKL_DPLL0, INTEL_DPLL_ALWAYS_ON }, +- { "DPLL 1", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 }, +- { "DPLL 2", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 }, +- { "DPLL 3", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL3, 0 }, +- { }, ++ { .name = "DPLL 0", .funcs = &skl_ddi_dpll0_funcs, .id = DPLL_ID_SKL_DPLL0, ++ .flags = INTEL_DPLL_ALWAYS_ON, }, ++ { .name = "DPLL 1", .funcs = &skl_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL1, }, ++ { .name = "DPLL 2", .funcs = &skl_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL2, }, ++ { .name = "DPLL 3", .funcs = &skl_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL3, }, ++ {} + }; + + static const struct intel_dpll_mgr skl_pll_mgr = { +@@ -2376,10 +2380,10 @@ static const struct intel_shared_dpll_fu + }; + + static const struct dpll_info bxt_plls[] = { +- { "PORT PLL A", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL0, 0 }, +- { "PORT PLL B", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 }, +- { "PORT PLL C", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 }, +- { }, ++ { .name = "PORT PLL A", .funcs = &bxt_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL0, }, ++ { .name = "PORT PLL B", .funcs = &bxt_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL1, }, ++ { .name = "PORT PLL C", .funcs = &bxt_ddi_pll_funcs, .id = DPLL_ID_SKL_DPLL2, }, ++ {} + }; + + static const struct intel_dpll_mgr bxt_pll_mgr = { +@@ -4014,14 +4018,14 @@ static const struct intel_shared_dpll_fu + }; + + static const struct dpll_info icl_plls[] = { +- { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 }, +- { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 }, +- { "TBT PLL", &tbt_pll_funcs, DPLL_ID_ICL_TBTPLL, 0 }, +- { "MG PLL 1", &mg_pll_funcs, DPLL_ID_ICL_MGPLL1, 0 }, +- { "MG PLL 2", &mg_pll_funcs, DPLL_ID_ICL_MGPLL2, 0 }, +- { "MG PLL 3", &mg_pll_funcs, DPLL_ID_ICL_MGPLL3, 0 }, +- { "MG PLL 4", &mg_pll_funcs, DPLL_ID_ICL_MGPLL4, 0 }, +- { }, ++ { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, }, ++ { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, }, ++ { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, }, ++ { .name = "MG PLL 1", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, }, ++ { .name = "MG PLL 2", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, }, ++ { .name = "MG PLL 3", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, }, ++ { .name = "MG PLL 4", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, }, ++ {} + }; + + static const struct intel_dpll_mgr icl_pll_mgr = { +@@ -4035,10 +4039,10 @@ static const struct intel_dpll_mgr icl_p + }; + + static const struct dpll_info ehl_plls[] = { +- { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 }, +- { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 }, +- { "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 }, +- { }, ++ { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, }, ++ { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, }, ++ { .name = "DPLL 4", .funcs = &combo_pll_funcs, .id = DPLL_ID_EHL_DPLL4, }, ++ {} + }; + + static const struct intel_dpll_mgr ehl_pll_mgr = { +@@ -4058,16 +4062,16 @@ static const struct intel_shared_dpll_fu + }; + + static const struct dpll_info tgl_plls[] = { +- { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 }, +- { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 }, +- { "TBT PLL", &tbt_pll_funcs, DPLL_ID_ICL_TBTPLL, 0 }, +- { "TC PLL 1", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL1, 0 }, +- { "TC PLL 2", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL2, 0 }, +- { "TC PLL 3", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL3, 0 }, +- { "TC PLL 4", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL4, 0 }, +- { "TC PLL 5", &dkl_pll_funcs, DPLL_ID_TGL_MGPLL5, 0 }, +- { "TC PLL 6", &dkl_pll_funcs, DPLL_ID_TGL_MGPLL6, 0 }, +- { }, ++ { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, }, ++ { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, }, ++ { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, }, ++ { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, }, ++ { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, }, ++ { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, }, ++ { .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, }, ++ { .name = "TC PLL 5", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL5, }, ++ { .name = "TC PLL 6", .funcs = &dkl_pll_funcs, .id = DPLL_ID_TGL_MGPLL6, }, ++ {} + }; + + static const struct intel_dpll_mgr tgl_pll_mgr = { +@@ -4081,10 +4085,10 @@ static const struct intel_dpll_mgr tgl_p + }; + + static const struct dpll_info rkl_plls[] = { +- { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 }, +- { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 }, +- { "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 }, +- { }, ++ { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, }, ++ { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, }, ++ { .name = "DPLL 4", .funcs = &combo_pll_funcs, .id = DPLL_ID_EHL_DPLL4, }, ++ {} + }; + + static const struct intel_dpll_mgr rkl_pll_mgr = { +@@ -4097,11 +4101,11 @@ static const struct intel_dpll_mgr rkl_p + }; + + static const struct dpll_info dg1_plls[] = { +- { "DPLL 0", &combo_pll_funcs, DPLL_ID_DG1_DPLL0, 0 }, +- { "DPLL 1", &combo_pll_funcs, DPLL_ID_DG1_DPLL1, 0 }, +- { "DPLL 2", &combo_pll_funcs, DPLL_ID_DG1_DPLL2, 0 }, +- { "DPLL 3", &combo_pll_funcs, DPLL_ID_DG1_DPLL3, 0 }, +- { }, ++ { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_DG1_DPLL0, }, ++ { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_DG1_DPLL1, }, ++ { .name = "DPLL 2", .funcs = &combo_pll_funcs, .id = DPLL_ID_DG1_DPLL2, }, ++ { .name = "DPLL 3", .funcs = &combo_pll_funcs, .id = DPLL_ID_DG1_DPLL3, }, ++ {} + }; + + static const struct intel_dpll_mgr dg1_pll_mgr = { +@@ -4114,11 +4118,11 @@ static const struct intel_dpll_mgr dg1_p + }; + + static const struct dpll_info adls_plls[] = { +- { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 }, +- { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 }, +- { "DPLL 2", &combo_pll_funcs, DPLL_ID_DG1_DPLL2, 0 }, +- { "DPLL 3", &combo_pll_funcs, DPLL_ID_DG1_DPLL3, 0 }, +- { }, ++ { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, }, ++ { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, }, ++ { .name = "DPLL 2", .funcs = &combo_pll_funcs, .id = DPLL_ID_DG1_DPLL2, }, ++ { .name = "DPLL 3", .funcs = &combo_pll_funcs, .id = DPLL_ID_DG1_DPLL3, }, ++ {} + }; + + static const struct intel_dpll_mgr adls_pll_mgr = { +@@ -4131,14 +4135,14 @@ static const struct intel_dpll_mgr adls_ + }; + + static const struct dpll_info adlp_plls[] = { +- { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 }, +- { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 }, +- { "TBT PLL", &tbt_pll_funcs, DPLL_ID_ICL_TBTPLL, 0 }, +- { "TC PLL 1", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL1, 0 }, +- { "TC PLL 2", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL2, 0 }, +- { "TC PLL 3", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL3, 0 }, +- { "TC PLL 4", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL4, 0 }, +- { }, ++ { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, }, ++ { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, }, ++ { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, }, ++ { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, }, ++ { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, }, ++ { .name = "TC PLL 3", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, }, ++ { .name = "TC PLL 4", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, }, ++ {} + }; + + static const struct intel_dpll_mgr adlp_pll_mgr = { diff --git a/queue-6.7/perf-top-use-evsel-s-cpus-to-replace-user_requested_cpus.patch b/queue-6.7/perf-top-use-evsel-s-cpus-to-replace-user_requested_cpus.patch new file mode 100644 index 00000000000..809b3ebefb0 --- /dev/null +++ b/queue-6.7/perf-top-use-evsel-s-cpus-to-replace-user_requested_cpus.patch @@ -0,0 +1,63 @@ +From 5fa695e7da4975e8d21ce49f3718d6cf00ecb75e Mon Sep 17 00:00:00 2001 +From: Kan Liang +Date: Thu, 14 Dec 2023 06:46:11 -0800 +Subject: perf top: Use evsel's cpus to replace user_requested_cpus + +From: Kan Liang + +commit 5fa695e7da4975e8d21ce49f3718d6cf00ecb75e upstream. + +perf top errors out on a hybrid machine + $perf top + + Error: + The cycles:P event is not supported. + +The perf top expects that the "cycles" is collected on all CPUs in the +system. But for hybrid there is no single "cycles" event which can cover +all CPUs. Perf has to split it into two cycles events, e.g., +cpu_core/cycles/ and cpu_atom/cycles/. Each event has its own CPU mask. +If a event is opened on the unsupported CPU. The open fails. That's the +reason of the above error out. + +Perf should only open the cycles event on the corresponding CPU. The +commit ef91871c960e ("perf evlist: Propagate user CPU maps intersecting +core PMU maps") intersect the requested CPU map with the CPU map of the +PMU. Use the evsel's cpus to replace user_requested_cpus. + +The evlist's threads are also propagated to the evsel's threads in +__perf_evlist__propagate_maps(). For a system-wide event, perf appends +a dummy event and assign it to the evsel's threads. For a per-thread +event, the evlist's thread_map is assigned to the evsel's threads. The +same as the other tools, e.g., perf record, using the evsel's threads +when opening an event. + +Reported-by: Arnaldo Carvalho de Melo +Reviewed-by: Ian Rogers +Signed-off-by: Kan Liang +Tested-by: Arnaldo Carvalho de Melo +Cc: Hector Martin +Cc: Marc Zyngier +Cc: Mark Rutland +Cc: Namhyung Kim +Closes: https://lore.kernel.org/linux-perf-users/ZXNnDrGKXbEELMXV@kernel.org/ +Link: https://lore.kernel.org/r/20231214144612.1092028-1-kan.liang@linux.intel.com +Signed-off-by: Arnaldo Carvalho de Melo +Signed-off-by: Greg Kroah-Hartman +--- + tools/perf/builtin-top.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/tools/perf/builtin-top.c ++++ b/tools/perf/builtin-top.c +@@ -1027,8 +1027,8 @@ static int perf_top__start_counters(stru + + evlist__for_each_entry(evlist, counter) { + try_again: +- if (evsel__open(counter, top->evlist->core.user_requested_cpus, +- top->evlist->core.threads) < 0) { ++ if (evsel__open(counter, counter->core.cpus, ++ counter->core.threads) < 0) { + + /* + * Specially handle overwrite fall back. diff --git a/queue-6.7/series b/queue-6.7/series index 37a86e0ab85..750010890f2 100644 --- a/queue-6.7/series +++ b/queue-6.7/series @@ -321,3 +321,10 @@ selftests-mm-fix-build-with-_fortify_source.patch btrfs-do-not-skip-re-registration-for-the-mounted-device.patch mfd-intel-lpss-switch-to-generalized-quirk-table.patch mfd-intel-lpss-introduce-quirk_clock_divider_unity-for-xps-9530.patch +perf-top-use-evsel-s-cpus-to-replace-user_requested_cpus.patch +drm-i915-stop-printing-pipe-name-as-hex.patch +drm-i915-use-named-initializers-for-dpll-info.patch +drm-i915-replace-a-memset-with-zero-initialization.patch +drm-i915-try-to-preserve-the-current-shared_dpll-for-fastset-on-type-c-ports.patch +drm-i915-include-the-pll-name-in-the-debug-messages.patch +drm-i915-suppress-old-pll-pipe_mask-checks-for-mg-tc-tbt-plls.patch