From: Greg Kroah-Hartman Date: Wed, 19 Aug 2020 10:30:10 +0000 (+0200) Subject: 5.7-stable patches X-Git-Tag: v4.14.194~56 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=494ce8d552e1ea762ba2ffb9b45e0aaff18045e6;p=thirdparty%2Fkernel%2Fstable-queue.git 5.7-stable patches added patches: pci-add-device-even-if-driver-attach-failed.patch pci-ats-add-pci_pri_supported-to-check-device-or-associated-pf.patch pci-mark-amd-navi10-gpu-rev-0x00-ats-as-broken.patch pci-qcom-add-support-for-tx-term-offset-for-rev-2.1.0.patch pci-qcom-define-some-parf-params-needed-for-ipq8064-soc.patch --- diff --git a/queue-5.7/pci-add-device-even-if-driver-attach-failed.patch b/queue-5.7/pci-add-device-even-if-driver-attach-failed.patch new file mode 100644 index 00000000000..9b3073dd43a --- /dev/null +++ b/queue-5.7/pci-add-device-even-if-driver-attach-failed.patch @@ -0,0 +1,46 @@ +From 2194bc7c39610be7cabe7456c5f63a570604f015 Mon Sep 17 00:00:00 2001 +From: Rajat Jain +Date: Mon, 6 Jul 2020 16:32:40 -0700 +Subject: PCI: Add device even if driver attach failed + +From: Rajat Jain + +commit 2194bc7c39610be7cabe7456c5f63a570604f015 upstream. + +device_attach() returning failure indicates a driver error while trying to +probe the device. In such a scenario, the PCI device should still be added +in the system and be visible to the user. + +When device_attach() fails, merely warn about it and keep the PCI device in +the system. + +This partially reverts ab1a187bba5c ("PCI: Check device_attach() return +value always"). + +Link: https://lore.kernel.org/r/20200706233240.3245512-1-rajatja@google.com +Signed-off-by: Rajat Jain +Signed-off-by: Bjorn Helgaas +Reviewed-by: Greg Kroah-Hartman +Cc: stable@vger.kernel.org # v4.6+ +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/pci/bus.c | 6 +----- + 1 file changed, 1 insertion(+), 5 deletions(-) + +--- a/drivers/pci/bus.c ++++ b/drivers/pci/bus.c +@@ -322,12 +322,8 @@ void pci_bus_add_device(struct pci_dev * + + dev->match_driver = true; + retval = device_attach(&dev->dev); +- if (retval < 0 && retval != -EPROBE_DEFER) { ++ if (retval < 0 && retval != -EPROBE_DEFER) + pci_warn(dev, "device attach failed (%d)\n", retval); +- pci_proc_detach_device(dev); +- pci_remove_sysfs_dev_files(dev); +- return; +- } + + pci_dev_assign_added(dev, true); + } diff --git a/queue-5.7/pci-ats-add-pci_pri_supported-to-check-device-or-associated-pf.patch b/queue-5.7/pci-ats-add-pci_pri_supported-to-check-device-or-associated-pf.patch new file mode 100644 index 00000000000..44569713ae8 --- /dev/null +++ b/queue-5.7/pci-ats-add-pci_pri_supported-to-check-device-or-associated-pf.patch @@ -0,0 +1,81 @@ +From 3f9a7a13fe4cb6e119e4e4745fbf975d30bfac9b Mon Sep 17 00:00:00 2001 +From: Ashok Raj +Date: Thu, 23 Jul 2020 15:37:29 -0700 +Subject: PCI/ATS: Add pci_pri_supported() to check device or associated PF + +From: Ashok Raj + +commit 3f9a7a13fe4cb6e119e4e4745fbf975d30bfac9b upstream. + +For SR-IOV, the PF PRI is shared between the PF and any associated VFs, and +the PRI Capability is allowed for PFs but not for VFs. Searching for the +PRI Capability on a VF always fails, even if its associated PF supports +PRI. + +Add pci_pri_supported() to check whether device or its associated PF +supports PRI. + +[bhelgaas: commit log, avoid "!!"] +Fixes: b16d0cb9e2fc ("iommu/vt-d: Always enable PASID/PRI PCI capabilities before ATS") +Link: https://lore.kernel.org/r/1595543849-19692-1-git-send-email-ashok.raj@intel.com +Signed-off-by: Ashok Raj +Signed-off-by: Bjorn Helgaas +Reviewed-by: Lu Baolu +Acked-by: Joerg Roedel +Cc: stable@vger.kernel.org # v4.4+ +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/iommu/intel-iommu.c | 2 +- + drivers/pci/ats.c | 15 +++++++++++++++ + include/linux/pci-ats.h | 4 ++++ + 3 files changed, 20 insertions(+), 1 deletion(-) + +--- a/drivers/iommu/intel-iommu.c ++++ b/drivers/iommu/intel-iommu.c +@@ -2645,7 +2645,7 @@ static struct dmar_domain *dmar_insert_o + } + + if (info->ats_supported && ecap_prs(iommu->ecap) && +- pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI)) ++ pci_pri_supported(pdev)) + info->pri_supported = 1; + } + } +--- a/drivers/pci/ats.c ++++ b/drivers/pci/ats.c +@@ -309,6 +309,21 @@ int pci_prg_resp_pasid_required(struct p + + return pdev->pasid_required; + } ++ ++/** ++ * pci_pri_supported - Check if PRI is supported. ++ * @pdev: PCI device structure ++ * ++ * Returns true if PRI capability is present, false otherwise. ++ */ ++bool pci_pri_supported(struct pci_dev *pdev) ++{ ++ /* VFs share the PF PRI */ ++ if (pci_physfn(pdev)->pri_cap) ++ return true; ++ return false; ++} ++EXPORT_SYMBOL_GPL(pci_pri_supported); + #endif /* CONFIG_PCI_PRI */ + + #ifdef CONFIG_PCI_PASID +--- a/include/linux/pci-ats.h ++++ b/include/linux/pci-ats.h +@@ -25,6 +25,10 @@ int pci_enable_pri(struct pci_dev *pdev, + void pci_disable_pri(struct pci_dev *pdev); + int pci_reset_pri(struct pci_dev *pdev); + int pci_prg_resp_pasid_required(struct pci_dev *pdev); ++bool pci_pri_supported(struct pci_dev *pdev); ++#else ++static inline bool pci_pri_supported(struct pci_dev *pdev) ++{ return false; } + #endif /* CONFIG_PCI_PRI */ + + #ifdef CONFIG_PCI_PASID diff --git a/queue-5.7/pci-mark-amd-navi10-gpu-rev-0x00-ats-as-broken.patch b/queue-5.7/pci-mark-amd-navi10-gpu-rev-0x00-ats-as-broken.patch new file mode 100644 index 00000000000..d723c6ec666 --- /dev/null +++ b/queue-5.7/pci-mark-amd-navi10-gpu-rev-0x00-ats-as-broken.patch @@ -0,0 +1,56 @@ +From 45beb31d3afb651bb5c41897e46bd4fa9980c51c Mon Sep 17 00:00:00 2001 +From: Kai-Heng Feng +Date: Tue, 28 Jul 2020 18:45:53 +0800 +Subject: PCI: Mark AMD Navi10 GPU rev 0x00 ATS as broken + +From: Kai-Heng Feng + +commit 45beb31d3afb651bb5c41897e46bd4fa9980c51c upstream. + +We are seeing AMD Radeon Pro W5700 doesn't work when IOMMU is enabled: + + iommu ivhd0: AMD-Vi: Event logged [IOTLB_INV_TIMEOUT device=63:00.0 address=0x42b5b01a0] + iommu ivhd0: AMD-Vi: Event logged [IOTLB_INV_TIMEOUT device=63:00.0 address=0x42b5b01c0] + +The error also makes graphics driver fail to probe the device. + +It appears to be the same issue as commit 5e89cd303e3a ("PCI: Mark AMD +Navi14 GPU rev 0xc5 ATS as broken") addresses, and indeed the same ATS +quirk can workaround the issue. + +See-also: 5e89cd303e3a ("PCI: Mark AMD Navi14 GPU rev 0xc5 ATS as broken") +See-also: d28ca864c493 ("PCI: Mark AMD Stoney Radeon R7 GPU ATS as broken") +See-also: 9b44b0b09dec ("PCI: Mark AMD Stoney GPU ATS as broken") +Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=208725 +Link: https://lore.kernel.org/r/20200728104554.28927-1-kai.heng.feng@canonical.com +Signed-off-by: Kai-Heng Feng +Signed-off-by: Bjorn Helgaas +Acked-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/pci/quirks.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +--- a/drivers/pci/quirks.c ++++ b/drivers/pci/quirks.c +@@ -5207,7 +5207,8 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SE + */ + static void quirk_amd_harvest_no_ats(struct pci_dev *pdev) + { +- if (pdev->device == 0x7340 && pdev->revision != 0xc5) ++ if ((pdev->device == 0x7312 && pdev->revision != 0x00) || ++ (pdev->device == 0x7340 && pdev->revision != 0xc5)) + return; + + pci_info(pdev, "disabling ATS\n"); +@@ -5218,6 +5219,8 @@ static void quirk_amd_harvest_no_ats(str + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats); + /* AMD Iceland dGPU */ + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats); ++/* AMD Navi10 dGPU */ ++DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats); + /* AMD Navi14 dGPU */ + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats); + #endif /* CONFIG_PCI_ATS */ diff --git a/queue-5.7/pci-qcom-add-support-for-tx-term-offset-for-rev-2.1.0.patch b/queue-5.7/pci-qcom-add-support-for-tx-term-offset-for-rev-2.1.0.patch new file mode 100644 index 00000000000..8f5a89b360f --- /dev/null +++ b/queue-5.7/pci-qcom-add-support-for-tx-term-offset-for-rev-2.1.0.patch @@ -0,0 +1,61 @@ +From de3c4bf648975ea0b1d344d811e9b0748907b47c Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Mon, 15 Jun 2020 23:06:04 +0200 +Subject: PCI: qcom: Add support for tx term offset for rev 2.1.0 + +From: Ansuel Smith + +commit de3c4bf648975ea0b1d344d811e9b0748907b47c upstream. + +Add tx term offset support to pcie qcom driver need in some revision of +the ipq806x SoC. Ipq8064 needs tx term offset set to 7. + +Link: https://lore.kernel.org/r/20200615210608.21469-9-ansuelsmth@gmail.com +Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") +Signed-off-by: Sham Muthayyan +Signed-off-by: Ansuel Smith +Signed-off-by: Lorenzo Pieralisi +Acked-by: Stanimir Varbanov +Cc: stable@vger.kernel.org # v4.5+ +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/pci/controller/dwc/pcie-qcom.c | 17 ++++++++++++++++- + 1 file changed, 16 insertions(+), 1 deletion(-) + +--- a/drivers/pci/controller/dwc/pcie-qcom.c ++++ b/drivers/pci/controller/dwc/pcie-qcom.c +@@ -45,7 +45,13 @@ + #define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10 + + #define PCIE20_PARF_PHY_CTRL 0x40 ++#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16) ++#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16) ++ + #define PCIE20_PARF_PHY_REFCLK 0x4C ++#define PHY_REFCLK_SSP_EN BIT(16) ++#define PHY_REFCLK_USE_PAD BIT(12) ++ + #define PCIE20_PARF_DBI_BASE_ADDR 0x168 + #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C + #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174 +@@ -354,9 +360,18 @@ static int qcom_pcie_init_2_1_0(struct q + writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS); + } + ++ if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) { ++ /* set TX termination offset */ ++ val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); ++ val &= ~PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK; ++ val |= PHY_CTRL_PHY_TX0_TERM_OFFSET(7); ++ writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); ++ } ++ + /* enable external reference clock */ + val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK); +- val |= BIT(16); ++ val &= ~PHY_REFCLK_USE_PAD; ++ val |= PHY_REFCLK_SSP_EN; + writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK); + + ret = reset_control_deassert(res->phy_reset); diff --git a/queue-5.7/pci-qcom-define-some-parf-params-needed-for-ipq8064-soc.patch b/queue-5.7/pci-qcom-define-some-parf-params-needed-for-ipq8064-soc.patch new file mode 100644 index 00000000000..b05326a8f4f --- /dev/null +++ b/queue-5.7/pci-qcom-define-some-parf-params-needed-for-ipq8064-soc.patch @@ -0,0 +1,73 @@ +From 5149901e9e6deca487c01cc434a3ac4125c7b00b Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Mon, 15 Jun 2020 23:06:03 +0200 +Subject: PCI: qcom: Define some PARF params needed for ipq8064 SoC + +From: Ansuel Smith + +commit 5149901e9e6deca487c01cc434a3ac4125c7b00b upstream. + +Set some specific value for Tx De-Emphasis, Tx Swing and Rx equalization +needed on some ipq8064 based device (Netgear R7800 for example). Without +this the system locks on kernel load. + +Link: https://lore.kernel.org/r/20200615210608.21469-8-ansuelsmth@gmail.com +Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") +Signed-off-by: Ansuel Smith +Signed-off-by: Lorenzo Pieralisi +Reviewed-by: Rob Herring +Acked-by: Stanimir Varbanov +Cc: stable@vger.kernel.org # v4.5+ +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/pci/controller/dwc/pcie-qcom.c | 24 ++++++++++++++++++++++++ + 1 file changed, 24 insertions(+) + +--- a/drivers/pci/controller/dwc/pcie-qcom.c ++++ b/drivers/pci/controller/dwc/pcie-qcom.c +@@ -77,6 +77,18 @@ + #define DBI_RO_WR_EN 1 + + #define PERST_DELAY_US 1000 ++/* PARF registers */ ++#define PCIE20_PARF_PCS_DEEMPH 0x34 ++#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) ((x) << 16) ++#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) ((x) << 8) ++#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) ((x) << 0) ++ ++#define PCIE20_PARF_PCS_SWING 0x38 ++#define PCS_SWING_TX_SWING_FULL(x) ((x) << 8) ++#define PCS_SWING_TX_SWING_LOW(x) ((x) << 0) ++ ++#define PCIE20_PARF_CONFIG_BITS 0x50 ++#define PHY_RX0_EQ(x) ((x) << 24) + + #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358 + #define SLV_ADDR_SPACE_SZ 0x10000000 +@@ -286,6 +298,7 @@ static int qcom_pcie_init_2_1_0(struct q + struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; + struct dw_pcie *pci = pcie->pci; + struct device *dev = pci->dev; ++ struct device_node *node = dev->of_node; + u32 val; + int ret; + +@@ -330,6 +343,17 @@ static int qcom_pcie_init_2_1_0(struct q + val &= ~BIT(0); + writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); + ++ if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) { ++ writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) | ++ PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) | ++ PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34), ++ pcie->parf + PCIE20_PARF_PCS_DEEMPH); ++ writel(PCS_SWING_TX_SWING_FULL(120) | ++ PCS_SWING_TX_SWING_LOW(120), ++ pcie->parf + PCIE20_PARF_PCS_SWING); ++ writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS); ++ } ++ + /* enable external reference clock */ + val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK); + val |= BIT(16); diff --git a/queue-5.7/series b/queue-5.7/series index 66249059811..458f334d387 100644 --- a/queue-5.7/series +++ b/queue-5.7/series @@ -2,3 +2,8 @@ smb3-warn-on-confusing-error-scenario-with-sec-krb5.patch genirq-affinity-make-affinity-setting-if-activated-opt-in.patch genirq-pm-always-unlock-irq-descriptor-in-rearm_wake_irq.patch pci-hotplug-acpi-fix-context-refcounting-in-acpiphp_grab_context.patch +pci-ats-add-pci_pri_supported-to-check-device-or-associated-pf.patch +pci-mark-amd-navi10-gpu-rev-0x00-ats-as-broken.patch +pci-add-device-even-if-driver-attach-failed.patch +pci-qcom-define-some-parf-params-needed-for-ipq8064-soc.patch +pci-qcom-add-support-for-tx-term-offset-for-rev-2.1.0.patch