From: segher Date: Mon, 4 Dec 2017 09:30:37 +0000 (+0000) Subject: lra: Clobbers in a parallel are earlyclobbers (PR83245) X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=49f6a314032bfe2d17b8d0e105374980814da702;p=thirdparty%2Fgcc.git lra: Clobbers in a parallel are earlyclobbers (PR83245) The documentation (rtl.texi) says: When a @code{clobber} expression for a register appears inside a @code{parallel} with other side effects, the register allocator guarantees that the register is unoccupied both before and after that insn if it is a hard register clobber. and at least the rs6000 backend relies on that (see PR83245). This patch restores that behaviour. Registers that are also used as operands in the instruction are not treated as earlyclobber, so such insns also still work (PR80818, an s390 testcase). PR rtl-optimization/83245 * lra.c (collect_non_operand_hard_regs): Treat clobbers of non-operand hard registers as earlyclobber, also if not in an asm. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@255377 138bc75d-0d04-0410-961f-82ee72b054a4 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 95496132a2bc..3b0f55ffe26e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2017-12-04 Segher Boessenkool + + PR rtl-optimization/83245 + * lra.c (collect_non_operand_hard_regs): Treat clobbers of non-operand + hard registers as earlyclobber, also if not in an asm. + 2017-12-04 Segher Boessenkool PR bootstrap/83265 diff --git a/gcc/lra.c b/gcc/lra.c index f49c50a40362..0d76eac3f3b5 100644 --- a/gcc/lra.c +++ b/gcc/lra.c @@ -888,14 +888,10 @@ collect_non_operand_hard_regs (rtx_insn *insn, rtx *x, list, OP_IN, false); break; case CLOBBER: - { - int code = INSN_CODE (insn); - /* We treat clobber of non-operand hard registers as early - clobber (the behavior is expected from asm). */ - list = collect_non_operand_hard_regs (insn, &XEXP (op, 0), data, - list, OP_OUT, code < 0); - break; - } + /* We treat clobber of non-operand hard registers as early clobber. */ + list = collect_non_operand_hard_regs (insn, &XEXP (op, 0), data, + list, OP_OUT, true); + break; case PRE_INC: case PRE_DEC: case POST_INC: case POST_DEC: list = collect_non_operand_hard_regs (insn, &XEXP (op, 0), data, list, OP_INOUT, false);