From: Jonathan Cameron Date: Fri, 1 Jul 2022 13:22:59 +0000 (+0100) Subject: hw/i386/pc: Always place CXL Memory Regions after device_memory X-Git-Tag: v7.1.0-rc0~1^2~13 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=4a447a710c523392b09391232d5a3dfb156a9d75;p=thirdparty%2Fqemu.git hw/i386/pc: Always place CXL Memory Regions after device_memory Previously broken_reserved_end was taken into account, but Igor Mammedov identified that this could lead to a clash between potential RAM being mapped in the region and CXL usage. Hence always add the size of the device_memory memory region. This only affects the case where the broken_reserved_end flag was set. Fixes: 6e4e3ae936e6 ("hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142)") Reported-by: Igor Mammedov Signed-off-by: Jonathan Cameron Message-Id: <20220701132300.2264-3-Jonathan.Cameron@huawei.com> Acked-by: Igor Mammedov Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- diff --git a/hw/i386/pc.c b/hw/i386/pc.c index d2b5823ffb2..46ab1dcb47b 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -922,10 +922,8 @@ void pc_memory_init(PCMachineState *pcms, hwaddr cxl_size = MiB; if (pcmc->has_reserved_memory && machine->device_memory->base) { - cxl_base = machine->device_memory->base; - if (!pcmc->broken_reserved_end) { - cxl_base += memory_region_size(&machine->device_memory->mr); - } + cxl_base = machine->device_memory->base + + memory_region_size(&machine->device_memory->mr); } else if (pcms->sgx_epc.size != 0) { cxl_base = sgx_epc_above_4g_end(&pcms->sgx_epc); } else {