From: Richard Henderson Date: Fri, 26 Jun 2020 03:31:28 +0000 (-0700) Subject: target/arm: Use mte_check1 for sve LD1R X-Git-Tag: v5.1.0-rc0~45^2~15 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=4ac430e1f1eb1d27913a9f800a5965b281ac1b76;p=thirdparty%2Fqemu.git target/arm: Use mte_check1 for sve LD1R Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200626033144.790098-31-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 4a613ca6892..4fa521989de 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4892,7 +4892,7 @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a) unsigned esz = dtype_esz[a->dtype]; unsigned msz = dtype_msz(a->dtype); TCGLabel *over = gen_new_label(); - TCGv_i64 temp; + TCGv_i64 temp, clean_addr; /* If the guarding predicate has no bits set, no load occurs. */ if (psz <= 8) { @@ -4915,7 +4915,9 @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a) /* Load the data. */ temp = tcg_temp_new_i64(); tcg_gen_addi_i64(temp, cpu_reg_sp(s, a->rn), a->imm << msz); - tcg_gen_qemu_ld_i64(temp, temp, get_mem_index(s), + clean_addr = gen_mte_check1(s, temp, false, true, msz); + + tcg_gen_qemu_ld_i64(temp, clean_addr, get_mem_index(s), s->be_data | dtype_mop[a->dtype]); /* Broadcast to *all* elements. */