From: TANG Tiancheng Date: Mon, 7 Oct 2024 02:57:00 +0000 (+0800) Subject: tcg/riscv: Enable native vector support for TCG host X-Git-Tag: v9.2.0-rc0~36^2~10 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=4b7868f8c21cebda86e81f3653e055aa2e87b591;p=thirdparty%2Fqemu.git tcg/riscv: Enable native vector support for TCG host Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson Message-ID: <20241007025700.47259-13-zhiwei_liu@linux.alibaba.com> Signed-off-by: Richard Henderson --- diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index e6d66cd1b91..334c37cbe6a 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -143,9 +143,9 @@ typedef enum { #define TCG_TARGET_HAS_tst 0 /* vector instructions */ -#define TCG_TARGET_HAS_v64 0 -#define TCG_TARGET_HAS_v128 0 -#define TCG_TARGET_HAS_v256 0 +#define TCG_TARGET_HAS_v64 (cpuinfo & CPUINFO_ZVE64X) +#define TCG_TARGET_HAS_v128 (cpuinfo & CPUINFO_ZVE64X) +#define TCG_TARGET_HAS_v256 (cpuinfo & CPUINFO_ZVE64X) #define TCG_TARGET_HAS_andc_vec 0 #define TCG_TARGET_HAS_orc_vec 0 #define TCG_TARGET_HAS_nand_vec 0