From: Greg Kroah-Hartman Date: Tue, 27 Mar 2018 07:52:03 +0000 (+0200) Subject: 4.9-stable patches X-Git-Tag: v4.15.14~13 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=4c2bbe4b24787c07e707aa09789d2d6d1e6d62d9;p=thirdparty%2Fkernel%2Fstable-queue.git 4.9-stable patches added patches: perf-stat-fix-cvs-output-format-for-non-supported-counters.patch perf-x86-intel-don-t-accidentally-clear-high-bits-in-bdw_limit_period.patch perf-x86-intel-uncore-fix-multi-domain-pci-cha-enumeration-bug-on-skylake-servers.patch perf-x86-intel-uncore-fix-skylake-upi-event-format.patch --- diff --git a/queue-4.9/perf-stat-fix-cvs-output-format-for-non-supported-counters.patch b/queue-4.9/perf-stat-fix-cvs-output-format-for-non-supported-counters.patch new file mode 100644 index 00000000000..c7016db4921 --- /dev/null +++ b/queue-4.9/perf-stat-fix-cvs-output-format-for-non-supported-counters.patch @@ -0,0 +1,42 @@ +From 40c21898ba5372c14ef71717040529794a91ccc2 Mon Sep 17 00:00:00 2001 +From: Ilya Pronin +Date: Mon, 5 Mar 2018 22:43:53 -0800 +Subject: perf stat: Fix CVS output format for non-supported counters + +From: Ilya Pronin + +commit 40c21898ba5372c14ef71717040529794a91ccc2 upstream. + +When printing stats in CSV mode, 'perf stat' appends extra separators +when a counter is not supported: + +,,L1-dcache-store-misses,mesos/bd442f34-2b4a-47df-b966-9b281f9f56fc,0,100.00,,,, + +Which causes a failure when parsing fields. The numbers of separators +should be the same for each line, no matter if the counter is or not +supported. + +Signed-off-by: Ilya Pronin +Acked-by: Jiri Olsa +Cc: Andi Kleen +Link: http://lkml.kernel.org/r/20180306064353.31930-1-xiyou.wangcong@gmail.com +Fixes: 92a61f6412d3 ("perf stat: Implement CSV metrics output") +Signed-off-by: Cong Wang +Signed-off-by: Arnaldo Carvalho de Melo +Signed-off-by: Greg Kroah-Hartman + +--- + tools/perf/builtin-stat.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/tools/perf/builtin-stat.c ++++ b/tools/perf/builtin-stat.c +@@ -876,7 +876,7 @@ static void print_metric_csv(void *ctx, + char buf[64], *vals, *ends; + + if (unit == NULL || fmt == NULL) { +- fprintf(out, "%s%s%s%s", csv_sep, csv_sep, csv_sep, csv_sep); ++ fprintf(out, "%s%s", csv_sep, csv_sep); + return; + } + snprintf(buf, sizeof(buf), fmt, val); diff --git a/queue-4.9/perf-x86-intel-don-t-accidentally-clear-high-bits-in-bdw_limit_period.patch b/queue-4.9/perf-x86-intel-don-t-accidentally-clear-high-bits-in-bdw_limit_period.patch new file mode 100644 index 00000000000..0883d1c7354 --- /dev/null +++ b/queue-4.9/perf-x86-intel-don-t-accidentally-clear-high-bits-in-bdw_limit_period.patch @@ -0,0 +1,46 @@ +From e5ea9b54a055619160bbfe527ebb7d7191823d66 Mon Sep 17 00:00:00 2001 +From: Dan Carpenter +Date: Sat, 17 Mar 2018 14:52:16 +0300 +Subject: perf/x86/intel: Don't accidentally clear high bits in bdw_limit_period() + +From: Dan Carpenter + +commit e5ea9b54a055619160bbfe527ebb7d7191823d66 upstream. + +We intended to clear the lowest 6 bits but because of a type bug we +clear the high 32 bits as well. Andi says that periods are rarely more +than U32_MAX so this bug probably doesn't have a huge runtime impact. + +Signed-off-by: Dan Carpenter +Signed-off-by: Peter Zijlstra (Intel) +Cc: Alexander Shishkin +Cc: Arnaldo Carvalho de Melo +Cc: H. Peter Anvin +Cc: Jiri Olsa +Cc: Kan Liang +Cc: Linus Torvalds +Cc: Peter Zijlstra +Cc: Sebastian Andrzej Siewior +Cc: Stephane Eranian +Cc: Thomas Gleixner +Cc: Vince Weaver +Fixes: 294fe0f52a44 ("perf/x86/intel: Add INST_RETIRED.ALL workarounds") +Link: http://lkml.kernel.org/r/20180317115216.GB4035@mwanda +Signed-off-by: Ingo Molnar +Signed-off-by: Greg Kroah-Hartman + +--- + arch/x86/events/intel/core.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/x86/events/intel/core.c ++++ b/arch/x86/events/intel/core.c +@@ -3025,7 +3025,7 @@ static unsigned bdw_limit_period(struct + X86_CONFIG(.event=0xc0, .umask=0x01)) { + if (left < 128) + left = 128; +- left &= ~0x3fu; ++ left &= ~0x3fULL; + } + return left; + } diff --git a/queue-4.9/perf-x86-intel-uncore-fix-multi-domain-pci-cha-enumeration-bug-on-skylake-servers.patch b/queue-4.9/perf-x86-intel-uncore-fix-multi-domain-pci-cha-enumeration-bug-on-skylake-servers.patch new file mode 100644 index 00000000000..2242c8540ab --- /dev/null +++ b/queue-4.9/perf-x86-intel-uncore-fix-multi-domain-pci-cha-enumeration-bug-on-skylake-servers.patch @@ -0,0 +1,100 @@ +From 320b0651f32b830add6497fcdcfdcb6ae8c7b8a0 Mon Sep 17 00:00:00 2001 +From: Kan Liang +Date: Tue, 13 Mar 2018 11:51:34 -0700 +Subject: perf/x86/intel/uncore: Fix multi-domain PCI CHA enumeration bug on Skylake servers + +From: Kan Liang + +commit 320b0651f32b830add6497fcdcfdcb6ae8c7b8a0 upstream. + +The number of CHAs is miscalculated on multi-domain PCI Skylake server systems, +resulting in an uncore driver initialization error. + +Gary Kroening explains: + + "For systems with a single PCI segment, it is sufficient to look for the + bus number to change in order to determine that all of the CHa's have + been counted for a single socket. + + However, for multi PCI segment systems, each socket is given a new + segment and the bus number does NOT change. So looking only for the + bus number to change ends up counting all of the CHa's on all sockets + in the system. This leads to writing CPU MSRs beyond a valid range and + causes an error in ivbep_uncore_msr_init_box()." + +To fix this bug, query the number of CHAs from the CAPID6 register: +it should read bits 27:0 in the CAPID6 register located at +Device 30, Function 3, Offset 0x9C. These 28 bits form a bit vector +of available LLC slices and the CHAs that manage those slices. + +Reported-by: Kroening, Gary +Tested-by: Kroening, Gary +Signed-off-by: Kan Liang +Signed-off-by: Peter Zijlstra (Intel) +Reviewed-by: Andy Shevchenko +Cc: Alexander Shishkin +Cc: Arnaldo Carvalho de Melo +Cc: Jiri Olsa +Cc: Linus Torvalds +Cc: Peter Zijlstra +Cc: Stephane Eranian +Cc: Thomas Gleixner +Cc: Vince Weaver +Cc: abanman@hpe.com +Cc: dimitri.sivanich@hpe.com +Cc: hpa@zytor.com +Cc: mike.travis@hpe.com +Cc: russ.anderson@hpe.com +Fixes: cd34cd97b7b4 ("perf/x86/intel/uncore: Add Skylake server uncore support") +Link: http://lkml.kernel.org/r/1520967094-13219-1-git-send-email-kan.liang@linux.intel.com +Signed-off-by: Ingo Molnar +Signed-off-by: Greg Kroah-Hartman + +--- + arch/x86/events/intel/uncore_snbep.c | 31 +++++++++++++++++-------------- + 1 file changed, 17 insertions(+), 14 deletions(-) + +--- a/arch/x86/events/intel/uncore_snbep.c ++++ b/arch/x86/events/intel/uncore_snbep.c +@@ -3522,24 +3522,27 @@ static struct intel_uncore_type *skx_msr + NULL, + }; + ++/* ++ * To determine the number of CHAs, it should read bits 27:0 in the CAPID6 ++ * register which located at Device 30, Function 3, Offset 0x9C. PCI ID 0x2083. ++ */ ++#define SKX_CAPID6 0x9c ++#define SKX_CHA_BIT_MASK GENMASK(27, 0) ++ + static int skx_count_chabox(void) + { +- struct pci_dev *chabox_dev = NULL; +- int bus, count = 0; ++ struct pci_dev *dev = NULL; ++ u32 val = 0; + +- while (1) { +- chabox_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x208d, chabox_dev); +- if (!chabox_dev) +- break; +- if (count == 0) +- bus = chabox_dev->bus->number; +- if (bus != chabox_dev->bus->number) +- break; +- count++; +- } ++ dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x2083, dev); ++ if (!dev) ++ goto out; + +- pci_dev_put(chabox_dev); +- return count; ++ pci_read_config_dword(dev, SKX_CAPID6, &val); ++ val &= SKX_CHA_BIT_MASK; ++out: ++ pci_dev_put(dev); ++ return hweight32(val); + } + + void skx_uncore_cpu_init(void) diff --git a/queue-4.9/perf-x86-intel-uncore-fix-skylake-upi-event-format.patch b/queue-4.9/perf-x86-intel-uncore-fix-skylake-upi-event-format.patch new file mode 100644 index 00000000000..cfb9943480f --- /dev/null +++ b/queue-4.9/perf-x86-intel-uncore-fix-skylake-upi-event-format.patch @@ -0,0 +1,41 @@ +From 317660940fd9dddd3201c2f92e25c27902c753fa Mon Sep 17 00:00:00 2001 +From: Kan Liang +Date: Fri, 2 Mar 2018 07:22:30 -0800 +Subject: perf/x86/intel/uncore: Fix Skylake UPI event format + +From: Kan Liang + +commit 317660940fd9dddd3201c2f92e25c27902c753fa upstream. + +There is no event extension (bit 21) for SKX UPI, so +use 'event' instead of 'event_ext'. + +Reported-by: Stephane Eranian +Signed-off-by: Kan Liang +Cc: Alexander Shishkin +Cc: Arnaldo Carvalho de Melo +Cc: Jiri Olsa +Cc: Linus Torvalds +Cc: Peter Zijlstra +Cc: Thomas Gleixner +Cc: Vince Weaver +Fixes: cd34cd97b7b4 ("perf/x86/intel/uncore: Add Skylake server uncore support") +Link: http://lkml.kernel.org/r/1520004150-4855-1-git-send-email-kan.liang@linux.intel.com +Signed-off-by: Ingo Molnar +Signed-off-by: Greg Kroah-Hartman + +--- + arch/x86/events/intel/uncore_snbep.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/x86/events/intel/uncore_snbep.c ++++ b/arch/x86/events/intel/uncore_snbep.c +@@ -3566,7 +3566,7 @@ static struct intel_uncore_type skx_unco + }; + + static struct attribute *skx_upi_uncore_formats_attr[] = { +- &format_attr_event_ext.attr, ++ &format_attr_event.attr, + &format_attr_umask_ext.attr, + &format_attr_edge.attr, + &format_attr_inv.attr, diff --git a/queue-4.9/series b/queue-4.9/series index 113ebb9ad6b..b4590e6fed8 100644 --- a/queue-4.9/series +++ b/queue-4.9/series @@ -51,3 +51,7 @@ kvm-x86-fix-icebp-instruction-handling.patch x86-build-64-force-the-linker-to-use-2mb-page-size.patch x86-boot-64-verify-alignment-of-the-load-segment.patch x86-entry-64-don-t-use-ist-entry-for-bp-stack.patch +perf-x86-intel-uncore-fix-skylake-upi-event-format.patch +perf-stat-fix-cvs-output-format-for-non-supported-counters.patch +perf-x86-intel-don-t-accidentally-clear-high-bits-in-bdw_limit_period.patch +perf-x86-intel-uncore-fix-multi-domain-pci-cha-enumeration-bug-on-skylake-servers.patch