From: Greg Kroah-Hartman Date: Thu, 20 May 2021 10:59:10 +0000 (+0200) Subject: drop arm-9058-1-cache-v7-refactor-v7_invalidate_l1-to-avo.patch from everywhere X-Git-Tag: v4.4.269~4 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=4d05b3bfe13ff4f5ebc1468abeff34956ea3f540;p=thirdparty%2Fkernel%2Fstable-queue.git drop arm-9058-1-cache-v7-refactor-v7_invalidate_l1-to-avo.patch from everywhere --- diff --git a/queue-4.14/arm-9058-1-cache-v7-refactor-v7_invalidate_l1-to-avo.patch b/queue-4.14/arm-9058-1-cache-v7-refactor-v7_invalidate_l1-to-avo.patch deleted file mode 100644 index 7c0230354b2..00000000000 --- a/queue-4.14/arm-9058-1-cache-v7-refactor-v7_invalidate_l1-to-avo.patch +++ /dev/null @@ -1,105 +0,0 @@ -From 0670bba9c44b03d61b7928da36c24d323b6dc367 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Thu, 11 Feb 2021 09:23:09 +0100 -Subject: ARM: 9058/1: cache-v7: refactor v7_invalidate_l1 to avoid clobbering - r5/r6 - -From: Ard Biesheuvel - -[ Upstream commit f9e7a99fb6b86aa6a00e53b34ee6973840e005aa ] - -The cache invalidation code in v7_invalidate_l1 can be tweaked to -re-read the associativity from CCSIDR, and keep the way identifier -component in a single register that is assigned in the outer loop. This -way, we need 2 registers less. - -Given that the number of sets is typically much larger than the -associativity, rearrange the code so that the outer loop has the fewer -number of iterations, ensuring that the re-read of CCSIDR only occurs a -handful of times in practice. - -Fix the whitespace while at it, and update the comment to indicate that -this code is no longer a clone of anything else. - -Acked-by: Nicolas Pitre -Signed-off-by: Ard Biesheuvel -Signed-off-by: Russell King -Signed-off-by: Sasha Levin ---- - arch/arm/mm/cache-v7.S | 51 +++++++++++++++++++++--------------------- - 1 file changed, 25 insertions(+), 26 deletions(-) - -diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S -index 50a70edbc863..08986397e5c7 100644 ---- a/arch/arm/mm/cache-v7.S -+++ b/arch/arm/mm/cache-v7.S -@@ -27,41 +27,40 @@ - * processor. We fix this by performing an invalidate, rather than a - * clean + invalidate, before jumping into the kernel. - * -- * This function is cloned from arch/arm/mach-tegra/headsmp.S, and needs -- * to be called for both secondary cores startup and primary core resume -- * procedures. -+ * This function needs to be called for both secondary cores startup and -+ * primary core resume procedures. - */ - ENTRY(v7_invalidate_l1) - mov r0, #0 - mcr p15, 2, r0, c0, c0, 0 - mrc p15, 1, r0, c0, c0, 0 - -- movw r1, #0x7fff -- and r2, r1, r0, lsr #13 -+ movw r3, #0x3ff -+ and r3, r3, r0, lsr #3 @ 'Associativity' in CCSIDR[12:3] -+ clz r1, r3 @ WayShift -+ mov r2, #1 -+ mov r3, r3, lsl r1 @ NumWays-1 shifted into bits [31:...] -+ movs r1, r2, lsl r1 @ #1 shifted left by same amount -+ moveq r1, #1 @ r1 needs value > 0 even if only 1 way - -- movw r1, #0x3ff -+ and r2, r0, #0x7 -+ add r2, r2, #4 @ SetShift - -- and r3, r1, r0, lsr #3 @ NumWays - 1 -- add r2, r2, #1 @ NumSets -+1: movw r4, #0x7fff -+ and r0, r4, r0, lsr #13 @ 'NumSets' in CCSIDR[27:13] - -- and r0, r0, #0x7 -- add r0, r0, #4 @ SetShift -- -- clz r1, r3 @ WayShift -- add r4, r3, #1 @ NumWays --1: sub r2, r2, #1 @ NumSets-- -- mov r3, r4 @ Temp = NumWays --2: subs r3, r3, #1 @ Temp-- -- mov r5, r3, lsl r1 -- mov r6, r2, lsl r0 -- orr r5, r5, r6 @ Reg = (Temp< -Date: Thu, 11 Feb 2021 09:23:09 +0100 -Subject: ARM: 9058/1: cache-v7: refactor v7_invalidate_l1 to avoid clobbering - r5/r6 - -From: Ard Biesheuvel - -[ Upstream commit f9e7a99fb6b86aa6a00e53b34ee6973840e005aa ] - -The cache invalidation code in v7_invalidate_l1 can be tweaked to -re-read the associativity from CCSIDR, and keep the way identifier -component in a single register that is assigned in the outer loop. This -way, we need 2 registers less. - -Given that the number of sets is typically much larger than the -associativity, rearrange the code so that the outer loop has the fewer -number of iterations, ensuring that the re-read of CCSIDR only occurs a -handful of times in practice. - -Fix the whitespace while at it, and update the comment to indicate that -this code is no longer a clone of anything else. - -Acked-by: Nicolas Pitre -Signed-off-by: Ard Biesheuvel -Signed-off-by: Russell King -Signed-off-by: Sasha Levin ---- - arch/arm/mm/cache-v7.S | 51 +++++++++++++++++++++--------------------- - 1 file changed, 25 insertions(+), 26 deletions(-) - -diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S -index 2149b47a0c5a..463965dc7922 100644 ---- a/arch/arm/mm/cache-v7.S -+++ b/arch/arm/mm/cache-v7.S -@@ -28,41 +28,40 @@ - * processor. We fix this by performing an invalidate, rather than a - * clean + invalidate, before jumping into the kernel. - * -- * This function is cloned from arch/arm/mach-tegra/headsmp.S, and needs -- * to be called for both secondary cores startup and primary core resume -- * procedures. -+ * This function needs to be called for both secondary cores startup and -+ * primary core resume procedures. - */ - ENTRY(v7_invalidate_l1) - mov r0, #0 - mcr p15, 2, r0, c0, c0, 0 - mrc p15, 1, r0, c0, c0, 0 - -- movw r1, #0x7fff -- and r2, r1, r0, lsr #13 -+ movw r3, #0x3ff -+ and r3, r3, r0, lsr #3 @ 'Associativity' in CCSIDR[12:3] -+ clz r1, r3 @ WayShift -+ mov r2, #1 -+ mov r3, r3, lsl r1 @ NumWays-1 shifted into bits [31:...] -+ movs r1, r2, lsl r1 @ #1 shifted left by same amount -+ moveq r1, #1 @ r1 needs value > 0 even if only 1 way - -- movw r1, #0x3ff -+ and r2, r0, #0x7 -+ add r2, r2, #4 @ SetShift - -- and r3, r1, r0, lsr #3 @ NumWays - 1 -- add r2, r2, #1 @ NumSets -+1: movw r4, #0x7fff -+ and r0, r4, r0, lsr #13 @ 'NumSets' in CCSIDR[27:13] - -- and r0, r0, #0x7 -- add r0, r0, #4 @ SetShift -- -- clz r1, r3 @ WayShift -- add r4, r3, #1 @ NumWays --1: sub r2, r2, #1 @ NumSets-- -- mov r3, r4 @ Temp = NumWays --2: subs r3, r3, #1 @ Temp-- -- mov r5, r3, lsl r1 -- mov r6, r2, lsl r0 -- orr r5, r5, r6 @ Reg = (Temp< -Date: Thu, 11 Feb 2021 09:23:09 +0100 -Subject: ARM: 9058/1: cache-v7: refactor v7_invalidate_l1 to avoid clobbering - r5/r6 - -From: Ard Biesheuvel - -[ Upstream commit f9e7a99fb6b86aa6a00e53b34ee6973840e005aa ] - -The cache invalidation code in v7_invalidate_l1 can be tweaked to -re-read the associativity from CCSIDR, and keep the way identifier -component in a single register that is assigned in the outer loop. This -way, we need 2 registers less. - -Given that the number of sets is typically much larger than the -associativity, rearrange the code so that the outer loop has the fewer -number of iterations, ensuring that the re-read of CCSIDR only occurs a -handful of times in practice. - -Fix the whitespace while at it, and update the comment to indicate that -this code is no longer a clone of anything else. - -Acked-by: Nicolas Pitre -Signed-off-by: Ard Biesheuvel -Signed-off-by: Russell King -Signed-off-by: Sasha Levin ---- - arch/arm/mm/cache-v7.S | 51 +++++++++++++++++++++--------------------- - 1 file changed, 25 insertions(+), 26 deletions(-) - -diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S -index 11d699af30ed..db568be45946 100644 ---- a/arch/arm/mm/cache-v7.S -+++ b/arch/arm/mm/cache-v7.S -@@ -27,41 +27,40 @@ - * processor. We fix this by performing an invalidate, rather than a - * clean + invalidate, before jumping into the kernel. - * -- * This function is cloned from arch/arm/mach-tegra/headsmp.S, and needs -- * to be called for both secondary cores startup and primary core resume -- * procedures. -+ * This function needs to be called for both secondary cores startup and -+ * primary core resume procedures. - */ - ENTRY(v7_invalidate_l1) - mov r0, #0 - mcr p15, 2, r0, c0, c0, 0 - mrc p15, 1, r0, c0, c0, 0 - -- movw r1, #0x7fff -- and r2, r1, r0, lsr #13 -+ movw r3, #0x3ff -+ and r3, r3, r0, lsr #3 @ 'Associativity' in CCSIDR[12:3] -+ clz r1, r3 @ WayShift -+ mov r2, #1 -+ mov r3, r3, lsl r1 @ NumWays-1 shifted into bits [31:...] -+ movs r1, r2, lsl r1 @ #1 shifted left by same amount -+ moveq r1, #1 @ r1 needs value > 0 even if only 1 way - -- movw r1, #0x3ff -+ and r2, r0, #0x7 -+ add r2, r2, #4 @ SetShift - -- and r3, r1, r0, lsr #3 @ NumWays - 1 -- add r2, r2, #1 @ NumSets -+1: movw r4, #0x7fff -+ and r0, r4, r0, lsr #13 @ 'NumSets' in CCSIDR[27:13] - -- and r0, r0, #0x7 -- add r0, r0, #4 @ SetShift -- -- clz r1, r3 @ WayShift -- add r4, r3, #1 @ NumWays --1: sub r2, r2, #1 @ NumSets-- -- mov r3, r4 @ Temp = NumWays --2: subs r3, r3, #1 @ Temp-- -- mov r5, r3, lsl r1 -- mov r6, r2, lsl r0 -- orr r5, r5, r6 @ Reg = (Temp< -Date: Thu, 11 Feb 2021 09:23:09 +0100 -Subject: ARM: 9058/1: cache-v7: refactor v7_invalidate_l1 to avoid clobbering - r5/r6 - -From: Ard Biesheuvel - -[ Upstream commit f9e7a99fb6b86aa6a00e53b34ee6973840e005aa ] - -The cache invalidation code in v7_invalidate_l1 can be tweaked to -re-read the associativity from CCSIDR, and keep the way identifier -component in a single register that is assigned in the outer loop. This -way, we need 2 registers less. - -Given that the number of sets is typically much larger than the -associativity, rearrange the code so that the outer loop has the fewer -number of iterations, ensuring that the re-read of CCSIDR only occurs a -handful of times in practice. - -Fix the whitespace while at it, and update the comment to indicate that -this code is no longer a clone of anything else. - -Acked-by: Nicolas Pitre -Signed-off-by: Ard Biesheuvel -Signed-off-by: Russell King -Signed-off-by: Sasha Levin ---- - arch/arm/mm/cache-v7.S | 51 +++++++++++++++++++++--------------------- - 1 file changed, 25 insertions(+), 26 deletions(-) - -diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S -index 11d699af30ed..db568be45946 100644 ---- a/arch/arm/mm/cache-v7.S -+++ b/arch/arm/mm/cache-v7.S -@@ -27,41 +27,40 @@ - * processor. We fix this by performing an invalidate, rather than a - * clean + invalidate, before jumping into the kernel. - * -- * This function is cloned from arch/arm/mach-tegra/headsmp.S, and needs -- * to be called for both secondary cores startup and primary core resume -- * procedures. -+ * This function needs to be called for both secondary cores startup and -+ * primary core resume procedures. - */ - ENTRY(v7_invalidate_l1) - mov r0, #0 - mcr p15, 2, r0, c0, c0, 0 - mrc p15, 1, r0, c0, c0, 0 - -- movw r1, #0x7fff -- and r2, r1, r0, lsr #13 -+ movw r3, #0x3ff -+ and r3, r3, r0, lsr #3 @ 'Associativity' in CCSIDR[12:3] -+ clz r1, r3 @ WayShift -+ mov r2, #1 -+ mov r3, r3, lsl r1 @ NumWays-1 shifted into bits [31:...] -+ movs r1, r2, lsl r1 @ #1 shifted left by same amount -+ moveq r1, #1 @ r1 needs value > 0 even if only 1 way - -- movw r1, #0x3ff -+ and r2, r0, #0x7 -+ add r2, r2, #4 @ SetShift - -- and r3, r1, r0, lsr #3 @ NumWays - 1 -- add r2, r2, #1 @ NumSets -+1: movw r4, #0x7fff -+ and r0, r4, r0, lsr #13 @ 'NumSets' in CCSIDR[27:13] - -- and r0, r0, #0x7 -- add r0, r0, #4 @ SetShift -- -- clz r1, r3 @ WayShift -- add r4, r3, #1 @ NumWays --1: sub r2, r2, #1 @ NumSets-- -- mov r3, r4 @ Temp = NumWays --2: subs r3, r3, #1 @ Temp-- -- mov r5, r3, lsl r1 -- mov r6, r2, lsl r0 -- orr r5, r5, r6 @ Reg = (Temp< -Date: Thu, 11 Feb 2021 09:23:09 +0100 -Subject: ARM: 9058/1: cache-v7: refactor v7_invalidate_l1 to avoid clobbering - r5/r6 - -From: Ard Biesheuvel - -[ Upstream commit f9e7a99fb6b86aa6a00e53b34ee6973840e005aa ] - -The cache invalidation code in v7_invalidate_l1 can be tweaked to -re-read the associativity from CCSIDR, and keep the way identifier -component in a single register that is assigned in the outer loop. This -way, we need 2 registers less. - -Given that the number of sets is typically much larger than the -associativity, rearrange the code so that the outer loop has the fewer -number of iterations, ensuring that the re-read of CCSIDR only occurs a -handful of times in practice. - -Fix the whitespace while at it, and update the comment to indicate that -this code is no longer a clone of anything else. - -Acked-by: Nicolas Pitre -Signed-off-by: Ard Biesheuvel -Signed-off-by: Russell King -Signed-off-by: Sasha Levin ---- - arch/arm/mm/cache-v7.S | 51 +++++++++++++++++++++--------------------- - 1 file changed, 25 insertions(+), 26 deletions(-) - -diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S -index dc8f152f3556..e3bc1d6e13d0 100644 ---- a/arch/arm/mm/cache-v7.S -+++ b/arch/arm/mm/cache-v7.S -@@ -33,41 +33,40 @@ icache_size: - * processor. We fix this by performing an invalidate, rather than a - * clean + invalidate, before jumping into the kernel. - * -- * This function is cloned from arch/arm/mach-tegra/headsmp.S, and needs -- * to be called for both secondary cores startup and primary core resume -- * procedures. -+ * This function needs to be called for both secondary cores startup and -+ * primary core resume procedures. - */ - ENTRY(v7_invalidate_l1) - mov r0, #0 - mcr p15, 2, r0, c0, c0, 0 - mrc p15, 1, r0, c0, c0, 0 - -- movw r1, #0x7fff -- and r2, r1, r0, lsr #13 -+ movw r3, #0x3ff -+ and r3, r3, r0, lsr #3 @ 'Associativity' in CCSIDR[12:3] -+ clz r1, r3 @ WayShift -+ mov r2, #1 -+ mov r3, r3, lsl r1 @ NumWays-1 shifted into bits [31:...] -+ movs r1, r2, lsl r1 @ #1 shifted left by same amount -+ moveq r1, #1 @ r1 needs value > 0 even if only 1 way - -- movw r1, #0x3ff -+ and r2, r0, #0x7 -+ add r2, r2, #4 @ SetShift - -- and r3, r1, r0, lsr #3 @ NumWays - 1 -- add r2, r2, #1 @ NumSets -+1: movw r4, #0x7fff -+ and r0, r4, r0, lsr #13 @ 'NumSets' in CCSIDR[27:13] - -- and r0, r0, #0x7 -- add r0, r0, #4 @ SetShift -- -- clz r1, r3 @ WayShift -- add r4, r3, #1 @ NumWays --1: sub r2, r2, #1 @ NumSets-- -- mov r3, r4 @ Temp = NumWays --2: subs r3, r3, #1 @ Temp-- -- mov r5, r3, lsl r1 -- mov r6, r2, lsl r0 -- orr r5, r5, r6 @ Reg = (Temp< -Date: Thu, 11 Feb 2021 09:23:09 +0100 -Subject: ARM: 9058/1: cache-v7: refactor v7_invalidate_l1 to avoid clobbering - r5/r6 - -From: Ard Biesheuvel - -[ Upstream commit f9e7a99fb6b86aa6a00e53b34ee6973840e005aa ] - -The cache invalidation code in v7_invalidate_l1 can be tweaked to -re-read the associativity from CCSIDR, and keep the way identifier -component in a single register that is assigned in the outer loop. This -way, we need 2 registers less. - -Given that the number of sets is typically much larger than the -associativity, rearrange the code so that the outer loop has the fewer -number of iterations, ensuring that the re-read of CCSIDR only occurs a -handful of times in practice. - -Fix the whitespace while at it, and update the comment to indicate that -this code is no longer a clone of anything else. - -Acked-by: Nicolas Pitre -Signed-off-by: Ard Biesheuvel -Signed-off-by: Russell King -Signed-off-by: Sasha Levin ---- - arch/arm/mm/cache-v7.S | 51 +++++++++++++++++++++--------------------- - 1 file changed, 25 insertions(+), 26 deletions(-) - -diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S -index dc8f152f3556..e3bc1d6e13d0 100644 ---- a/arch/arm/mm/cache-v7.S -+++ b/arch/arm/mm/cache-v7.S -@@ -33,41 +33,40 @@ icache_size: - * processor. We fix this by performing an invalidate, rather than a - * clean + invalidate, before jumping into the kernel. - * -- * This function is cloned from arch/arm/mach-tegra/headsmp.S, and needs -- * to be called for both secondary cores startup and primary core resume -- * procedures. -+ * This function needs to be called for both secondary cores startup and -+ * primary core resume procedures. - */ - ENTRY(v7_invalidate_l1) - mov r0, #0 - mcr p15, 2, r0, c0, c0, 0 - mrc p15, 1, r0, c0, c0, 0 - -- movw r1, #0x7fff -- and r2, r1, r0, lsr #13 -+ movw r3, #0x3ff -+ and r3, r3, r0, lsr #3 @ 'Associativity' in CCSIDR[12:3] -+ clz r1, r3 @ WayShift -+ mov r2, #1 -+ mov r3, r3, lsl r1 @ NumWays-1 shifted into bits [31:...] -+ movs r1, r2, lsl r1 @ #1 shifted left by same amount -+ moveq r1, #1 @ r1 needs value > 0 even if only 1 way - -- movw r1, #0x3ff -+ and r2, r0, #0x7 -+ add r2, r2, #4 @ SetShift - -- and r3, r1, r0, lsr #3 @ NumWays - 1 -- add r2, r2, #1 @ NumSets -+1: movw r4, #0x7fff -+ and r0, r4, r0, lsr #13 @ 'NumSets' in CCSIDR[27:13] - -- and r0, r0, #0x7 -- add r0, r0, #4 @ SetShift -- -- clz r1, r3 @ WayShift -- add r4, r3, #1 @ NumWays --1: sub r2, r2, #1 @ NumSets-- -- mov r3, r4 @ Temp = NumWays --2: subs r3, r3, #1 @ Temp-- -- mov r5, r3, lsl r1 -- mov r6, r2, lsl r0 -- orr r5, r5, r6 @ Reg = (Temp< -Date: Thu, 11 Feb 2021 09:23:09 +0100 -Subject: ARM: 9058/1: cache-v7: refactor v7_invalidate_l1 to avoid clobbering - r5/r6 - -From: Ard Biesheuvel - -[ Upstream commit f9e7a99fb6b86aa6a00e53b34ee6973840e005aa ] - -The cache invalidation code in v7_invalidate_l1 can be tweaked to -re-read the associativity from CCSIDR, and keep the way identifier -component in a single register that is assigned in the outer loop. This -way, we need 2 registers less. - -Given that the number of sets is typically much larger than the -associativity, rearrange the code so that the outer loop has the fewer -number of iterations, ensuring that the re-read of CCSIDR only occurs a -handful of times in practice. - -Fix the whitespace while at it, and update the comment to indicate that -this code is no longer a clone of anything else. - -Acked-by: Nicolas Pitre -Signed-off-by: Ard Biesheuvel -Signed-off-by: Russell King -Signed-off-by: Sasha Levin ---- - arch/arm/mm/cache-v7.S | 51 +++++++++++++++++++++--------------------- - 1 file changed, 25 insertions(+), 26 deletions(-) - -diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S -index 0ee8fc4b4672..8e69bf36a3ec 100644 ---- a/arch/arm/mm/cache-v7.S -+++ b/arch/arm/mm/cache-v7.S -@@ -33,41 +33,40 @@ icache_size: - * processor. We fix this by performing an invalidate, rather than a - * clean + invalidate, before jumping into the kernel. - * -- * This function is cloned from arch/arm/mach-tegra/headsmp.S, and needs -- * to be called for both secondary cores startup and primary core resume -- * procedures. -+ * This function needs to be called for both secondary cores startup and -+ * primary core resume procedures. - */ - ENTRY(v7_invalidate_l1) - mov r0, #0 - mcr p15, 2, r0, c0, c0, 0 - mrc p15, 1, r0, c0, c0, 0 - -- movw r1, #0x7fff -- and r2, r1, r0, lsr #13 -+ movw r3, #0x3ff -+ and r3, r3, r0, lsr #3 @ 'Associativity' in CCSIDR[12:3] -+ clz r1, r3 @ WayShift -+ mov r2, #1 -+ mov r3, r3, lsl r1 @ NumWays-1 shifted into bits [31:...] -+ movs r1, r2, lsl r1 @ #1 shifted left by same amount -+ moveq r1, #1 @ r1 needs value > 0 even if only 1 way - -- movw r1, #0x3ff -+ and r2, r0, #0x7 -+ add r2, r2, #4 @ SetShift - -- and r3, r1, r0, lsr #3 @ NumWays - 1 -- add r2, r2, #1 @ NumSets -+1: movw r4, #0x7fff -+ and r0, r4, r0, lsr #13 @ 'NumSets' in CCSIDR[27:13] - -- and r0, r0, #0x7 -- add r0, r0, #4 @ SetShift -- -- clz r1, r3 @ WayShift -- add r4, r3, #1 @ NumWays --1: sub r2, r2, #1 @ NumSets-- -- mov r3, r4 @ Temp = NumWays --2: subs r3, r3, #1 @ Temp-- -- mov r5, r3, lsl r1 -- mov r6, r2, lsl r0 -- orr r5, r5, r6 @ Reg = (Temp<