From: Greg Kroah-Hartman Date: Fri, 12 Feb 2010 01:09:06 +0000 (-0800) Subject: more .32 patches X-Git-Tag: v2.6.32.9~20 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=4d3fdb08703d9e12aca04b585c250c4db6e8262c;p=thirdparty%2Fkernel%2Fstable-queue.git more .32 patches --- diff --git a/queue-2.6.32/alsa-ctxfi-fix-ptp-address-initialization.patch b/queue-2.6.32/alsa-ctxfi-fix-ptp-address-initialization.patch new file mode 100644 index 00000000000..f8739b3fd6b --- /dev/null +++ b/queue-2.6.32/alsa-ctxfi-fix-ptp-address-initialization.patch @@ -0,0 +1,174 @@ +From 21956b61f594f7924d98240da74bc81c28601fa9 Mon Sep 17 00:00:00 2001 +From: Jaroslav Kysela +Date: Tue, 2 Feb 2010 19:58:25 +0100 +Subject: ALSA: ctxfi - fix PTP address initialization + +From: Jaroslav Kysela + +commit 21956b61f594f7924d98240da74bc81c28601fa9 upstream. + +After hours of debugging, I finally found the reason why some source +and runtime combination does not work. The PTP (page table pages) +address must be aligned. I am not sure how much, but alignment to +PAGE_SIZE is sufficient. Also, use ALSA's page allocation routines +to ensure proper virtual -> physical address translation. + +Signed-off-by: Jaroslav Kysela +Signed-off-by: Greg Kroah-Hartman + +--- + sound/pci/ctxfi/ctatc.c | 15 ++------------- + sound/pci/ctxfi/ctvmem.c | 38 ++++++++++++++++++-------------------- + sound/pci/ctxfi/ctvmem.h | 8 +++++--- + 3 files changed, 25 insertions(+), 36 deletions(-) + +--- a/sound/pci/ctxfi/ctatc.c ++++ b/sound/pci/ctxfi/ctatc.c +@@ -166,18 +166,7 @@ static void ct_unmap_audio_buffer(struct + + static unsigned long atc_get_ptp_phys(struct ct_atc *atc, int index) + { +- struct ct_vm *vm; +- void *kvirt_addr; +- unsigned long phys_addr; +- +- vm = atc->vm; +- kvirt_addr = vm->get_ptp_virt(vm, index); +- if (kvirt_addr == NULL) +- phys_addr = (~0UL); +- else +- phys_addr = virt_to_phys(kvirt_addr); +- +- return phys_addr; ++ return atc->vm->get_ptp_phys(atc->vm, index); + } + + static unsigned int convert_format(snd_pcm_format_t snd_format) +@@ -1669,7 +1658,7 @@ int __devinit ct_atc_create(struct snd_c + } + + /* Set up device virtual memory management object */ +- err = ct_vm_create(&atc->vm); ++ err = ct_vm_create(&atc->vm, pci); + if (err < 0) + goto error1; + +--- a/sound/pci/ctxfi/ctvmem.c ++++ b/sound/pci/ctxfi/ctvmem.c +@@ -138,7 +138,7 @@ ct_vm_map(struct ct_vm *vm, struct snd_p + return NULL; + } + +- ptp = vm->ptp[0]; ++ ptp = (unsigned long *)vm->ptp[0].area; + pte_start = (block->addr >> CT_PAGE_SHIFT); + pages = block->size >> CT_PAGE_SHIFT; + for (i = 0; i < pages; i++) { +@@ -158,25 +158,25 @@ static void ct_vm_unmap(struct ct_vm *vm + } + + /* * +- * return the host (kmalloced) addr of the @index-th device +- * page talbe page on success, or NULL on failure. +- * The first returned NULL indicates the termination. ++ * return the host physical addr of the @index-th device ++ * page table page on success, or ~0UL on failure. ++ * The first returned ~0UL indicates the termination. + * */ +-static void * +-ct_get_ptp_virt(struct ct_vm *vm, int index) ++static dma_addr_t ++ct_get_ptp_phys(struct ct_vm *vm, int index) + { +- void *addr; ++ dma_addr_t addr; + +- addr = (index >= CT_PTP_NUM) ? NULL : vm->ptp[index]; ++ addr = (index >= CT_PTP_NUM) ? ~0UL : vm->ptp[index].addr; + + return addr; + } + +-int ct_vm_create(struct ct_vm **rvm) ++int ct_vm_create(struct ct_vm **rvm, struct pci_dev *pci) + { + struct ct_vm *vm; + struct ct_vm_block *block; +- int i; ++ int i, err = 0; + + *rvm = NULL; + +@@ -188,23 +188,21 @@ int ct_vm_create(struct ct_vm **rvm) + + /* Allocate page table pages */ + for (i = 0; i < CT_PTP_NUM; i++) { +- vm->ptp[i] = kmalloc(PAGE_SIZE, GFP_KERNEL); +- if (!vm->ptp[i]) ++ err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, ++ snd_dma_pci_data(pci), ++ PAGE_SIZE, &vm->ptp[i]); ++ if (err < 0) + break; + } +- if (!i) { ++ if (err < 0) { + /* no page table pages are allocated */ +- kfree(vm); ++ ct_vm_destroy(vm); + return -ENOMEM; + } + vm->size = CT_ADDRS_PER_PAGE * i; +- /* Initialise remaining ptps */ +- for (; i < CT_PTP_NUM; i++) +- vm->ptp[i] = NULL; +- + vm->map = ct_vm_map; + vm->unmap = ct_vm_unmap; +- vm->get_ptp_virt = ct_get_ptp_virt; ++ vm->get_ptp_phys = ct_get_ptp_phys; + INIT_LIST_HEAD(&vm->unused); + INIT_LIST_HEAD(&vm->used); + block = kzalloc(sizeof(*block), GFP_KERNEL); +@@ -242,7 +240,7 @@ void ct_vm_destroy(struct ct_vm *vm) + + /* free allocated page table pages */ + for (i = 0; i < CT_PTP_NUM; i++) +- kfree(vm->ptp[i]); ++ snd_dma_free_pages(&vm->ptp[i]); + + vm->size = 0; + +--- a/sound/pci/ctxfi/ctvmem.h ++++ b/sound/pci/ctxfi/ctvmem.h +@@ -22,6 +22,8 @@ + + #include + #include ++#include ++#include + + /* The chip can handle the page table of 4k pages + * (emu20k1 can handle even 8k pages, but we don't use it right now) +@@ -41,7 +43,7 @@ struct snd_pcm_substream; + + /* Virtual memory management object for card device */ + struct ct_vm { +- void *ptp[CT_PTP_NUM]; /* Device page table pages */ ++ struct snd_dma_buffer ptp[CT_PTP_NUM]; /* Device page table pages */ + unsigned int size; /* Available addr space in bytes */ + struct list_head unused; /* List of unused blocks */ + struct list_head used; /* List of used blocks */ +@@ -52,10 +54,10 @@ struct ct_vm { + int size); + /* Unmap device logical addr area. */ + void (*unmap)(struct ct_vm *, struct ct_vm_block *block); +- void *(*get_ptp_virt)(struct ct_vm *vm, int index); ++ dma_addr_t (*get_ptp_phys)(struct ct_vm *vm, int index); + }; + +-int ct_vm_create(struct ct_vm **rvm); ++int ct_vm_create(struct ct_vm **rvm, struct pci_dev *pci); + void ct_vm_destroy(struct ct_vm *vm); + + #endif /* CTVMEM_H */ diff --git a/queue-2.6.32/drm-i915-add-hp-nx9020-samsungsx20s-to-acpi-lid-quirk-list.patch b/queue-2.6.32/drm-i915-add-hp-nx9020-samsungsx20s-to-acpi-lid-quirk-list.patch new file mode 100644 index 00000000000..36100042f8e --- /dev/null +++ b/queue-2.6.32/drm-i915-add-hp-nx9020-samsungsx20s-to-acpi-lid-quirk-list.patch @@ -0,0 +1,47 @@ +From 40f33a92100f4d9b6e85ad642100cfe42d7ff57d Mon Sep 17 00:00:00 2001 +From: Zhao Yakui +Date: Wed, 6 Jan 2010 13:30:36 +0800 +Subject: drm/i915: Add HP nx9020/SamsungSX20S to ACPI LID quirk list + +From: Zhao Yakui + +commit 40f33a92100f4d9b6e85ad642100cfe42d7ff57d upstream. + +The HP comaq nx9020/Samsung SX20S laptop always report that the LID status is +closed and we can't use it reliabily for LVDS detection. So add the two boxes +into the quirk list. + +http://bugzilla.kernel.org/show_bug.cgi?id=14957 +http://bugzilla.kernel.org/show_bug.cgi?id=14554 + +Signed-off-by: Zhao Yakui +Signed-off-by: Eric Anholt +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/intel_lvds.c | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +--- a/drivers/gpu/drm/i915/intel_lvds.c ++++ b/drivers/gpu/drm/i915/intel_lvds.c +@@ -602,6 +602,20 @@ static void intel_lvds_mode_set(struct d + /* Some lid devices report incorrect lid status, assume they're connected */ + static const struct dmi_system_id bad_lid_status[] = { + { ++ .ident = "Compaq nx9020", ++ .matches = { ++ DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), ++ DMI_MATCH(DMI_BOARD_NAME, "3084"), ++ }, ++ }, ++ { ++ .ident = "Samsung SX20S", ++ .matches = { ++ DMI_MATCH(DMI_SYS_VENDOR, "Phoenix Technologies LTD"), ++ DMI_MATCH(DMI_BOARD_NAME, "SX20S"), ++ }, ++ }, ++ { + .ident = "Aspire One", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Acer"), diff --git a/queue-2.6.32/drm-i915-add-malata-pc-81005-to-acpi-lid-quirk-list.patch b/queue-2.6.32/drm-i915-add-malata-pc-81005-to-acpi-lid-quirk-list.patch new file mode 100644 index 00000000000..228239f2456 --- /dev/null +++ b/queue-2.6.32/drm-i915-add-malata-pc-81005-to-acpi-lid-quirk-list.patch @@ -0,0 +1,40 @@ +From a3cb5195f6db58dbebd8a31b877ddce082c9b63d Mon Sep 17 00:00:00 2001 +From: Zhao Yakui +Date: Fri, 11 Dec 2009 09:26:10 +0800 +Subject: drm/i915: Add MALATA PC-81005 to ACPI LID quirk list + +From: Zhao Yakui + +commit a3cb5195f6db58dbebd8a31b877ddce082c9b63d upstream. + +The MALATA PC-81005 laptop always reports that the LID status is closed and we +can't use it reliabily for LVDS detection. So add this box into the quirk list. + +https://bugs.freedesktop.org/show_bug.cgi?id=25523 + +Signed-off-by: Zhao Yakui +Review-by: Jesse Barnes +Tested-by: Hector +Signed-off-by: Eric Anholt +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/intel_lvds.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/drivers/gpu/drm/i915/intel_lvds.c ++++ b/drivers/gpu/drm/i915/intel_lvds.c +@@ -622,6 +622,13 @@ static const struct dmi_system_id bad_li + DMI_MATCH(DMI_PRODUCT_NAME, "Aspire one"), + }, + }, ++ { ++ .ident = "PC-81005", ++ .matches = { ++ DMI_MATCH(DMI_SYS_VENDOR, "MALATA"), ++ DMI_MATCH(DMI_PRODUCT_NAME, "PC-81005"), ++ }, ++ }, + { } + }; + diff --git a/queue-2.6.32/drm-i915-disable-hotplug-detect-before-ironlake-crt-detect.patch b/queue-2.6.32/drm-i915-disable-hotplug-detect-before-ironlake-crt-detect.patch new file mode 100644 index 00000000000..583c5c3bd46 --- /dev/null +++ b/queue-2.6.32/drm-i915-disable-hotplug-detect-before-ironlake-crt-detect.patch @@ -0,0 +1,33 @@ +From eceb784cec4dc0fcc2993d9ee4a7c0d111ada80a Mon Sep 17 00:00:00 2001 +From: Zhenyu Wang +Date: Mon, 25 Jan 2010 10:35:16 +0800 +Subject: drm/i915: disable hotplug detect before Ironlake CRT detect + +From: Zhenyu Wang + +commit eceb784cec4dc0fcc2993d9ee4a7c0d111ada80a upstream. + +This tries to fix CRT detect loop hang seen on some Ironlake form +factor, to clear up hotplug detect state before taking CRT detect +to make sure next hotplug detect cycle is consistent. + +Signed-off-by: Zhenyu Wang +Signed-off-by: Eric Anholt +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/intel_crt.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/gpu/drm/i915/intel_crt.c ++++ b/drivers/gpu/drm/i915/intel_crt.c +@@ -185,6 +185,9 @@ static bool intel_igdng_crt_detect_hotpl + adpa = I915_READ(PCH_ADPA); + + adpa &= ~ADPA_CRT_HOTPLUG_MASK; ++ /* disable HPD first */ ++ I915_WRITE(PCH_ADPA, adpa); ++ (void)I915_READ(PCH_ADPA); + + adpa |= (ADPA_CRT_HOTPLUG_PERIOD_128 | + ADPA_CRT_HOTPLUG_WARMUP_10MS | diff --git a/queue-2.6.32/drm-i915-disable-sr-when-more-than-one-pipe-is-enabled.patch b/queue-2.6.32/drm-i915-disable-sr-when-more-than-one-pipe-is-enabled.patch new file mode 100644 index 00000000000..5efa9d2d7de --- /dev/null +++ b/queue-2.6.32/drm-i915-disable-sr-when-more-than-one-pipe-is-enabled.patch @@ -0,0 +1,59 @@ +From 33c5fd121eabbccc9103daf6cda36941eb3c349f Mon Sep 17 00:00:00 2001 +From: David John +Date: Wed, 27 Jan 2010 15:19:08 +0530 +Subject: drm/i915: Disable SR when more than one pipe is enabled + +From: David John + +commit 33c5fd121eabbccc9103daf6cda36941eb3c349f upstream. + +Self Refresh should be disabled on dual plane configs. Otherwise, as +the SR watermark is not calculated for such configs, switching to non +VGA mode causes FIFO underrun and display flicker. + +This fixes Korg Bug #14897. + +Signed-off-by: David John +Signed-off-by: Jesse Barnes +Signed-off-by: Eric Anholt +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/intel_display.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +--- a/drivers/gpu/drm/i915/intel_display.c ++++ b/drivers/gpu/drm/i915/intel_display.c +@@ -2538,6 +2538,10 @@ static void g4x_update_wm(struct drm_dev + sr_entries = roundup(sr_entries / cacheline_size, 1); + DRM_DEBUG("self-refresh entries: %d\n", sr_entries); + I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); ++ } else { ++ /* Turn off self refresh if both pipes are enabled */ ++ I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) ++ & ~FW_BLC_SELF_EN); + } + + DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n", +@@ -2581,6 +2585,10 @@ static void i965_update_wm(struct drm_de + srwm = 1; + srwm &= 0x3f; + I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); ++ } else { ++ /* Turn off self refresh if both pipes are enabled */ ++ I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) ++ & ~FW_BLC_SELF_EN); + } + + DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", +@@ -2649,6 +2657,10 @@ static void i9xx_update_wm(struct drm_de + if (srwm < 0) + srwm = 1; + I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f)); ++ } else { ++ /* Turn off self refresh if both pipes are enabled */ ++ I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) ++ & ~FW_BLC_SELF_EN); + } + + DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", diff --git a/queue-2.6.32/drm-i915-enable-self-refresh-on-965.patch b/queue-2.6.32/drm-i915-enable-self-refresh-on-965.patch new file mode 100644 index 00000000000..3ef285e4fef --- /dev/null +++ b/queue-2.6.32/drm-i915-enable-self-refresh-on-965.patch @@ -0,0 +1,65 @@ +From 1dc7546d1a73664e5d117715b214bea9cae5951c Mon Sep 17 00:00:00 2001 +From: Jesse Barnes +Date: Mon, 19 Oct 2009 10:08:17 +0900 +Subject: drm/i915: enable self-refresh on 965 + +From: Jesse Barnes + +commit 1dc7546d1a73664e5d117715b214bea9cae5951c upstream. + +Need to calculate the SR watermark and enable it. + +Signed-off-by: Jesse Barnes +Signed-off-by: Eric Anholt +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/intel_display.c | 32 ++++++++++++++++++++++++++++---- + 1 file changed, 28 insertions(+), 4 deletions(-) + +--- a/drivers/gpu/drm/i915/intel_display.c ++++ b/drivers/gpu/drm/i915/intel_display.c +@@ -2556,15 +2556,39 @@ static void g4x_update_wm(struct drm_dev + (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); + } + +-static void i965_update_wm(struct drm_device *dev, int unused, int unused2, +- int unused3, int unused4) ++static void i965_update_wm(struct drm_device *dev, int planea_clock, ++ int planeb_clock, int sr_hdisplay, int pixel_size) + { + struct drm_i915_private *dev_priv = dev->dev_private; ++ unsigned long line_time_us; ++ int sr_clock, sr_entries, srwm = 1; + +- DRM_DEBUG("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 8\n"); ++ /* Calc sr entries for one plane configs */ ++ if (sr_hdisplay && (!planea_clock || !planeb_clock)) { ++ /* self-refresh has much higher latency */ ++ const static int sr_latency_ns = 12000; ++ ++ sr_clock = planea_clock ? planea_clock : planeb_clock; ++ line_time_us = ((sr_hdisplay * 1000) / sr_clock); ++ ++ /* Use ns/us then divide to preserve precision */ ++ sr_entries = (((sr_latency_ns / line_time_us) + 1) * ++ pixel_size * sr_hdisplay) / 1000; ++ sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1); ++ DRM_DEBUG("self-refresh entries: %d\n", sr_entries); ++ srwm = I945_FIFO_SIZE - sr_entries; ++ if (srwm < 0) ++ srwm = 1; ++ srwm &= 0x3f; ++ I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); ++ } ++ ++ DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", ++ srwm); + + /* 965 has limitations... */ +- I915_WRITE(DSPFW1, (8 << 16) | (8 << 8) | (8 << 0)); ++ I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) | ++ (8 << 0)); + I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); + } + diff --git a/queue-2.6.32/drm-i915-fix-ddc-on-some-systems-by-clearing-bios-gmbus-setup.patch b/queue-2.6.32/drm-i915-fix-ddc-on-some-systems-by-clearing-bios-gmbus-setup.patch new file mode 100644 index 00000000000..8fc860833e8 --- /dev/null +++ b/queue-2.6.32/drm-i915-fix-ddc-on-some-systems-by-clearing-bios-gmbus-setup.patch @@ -0,0 +1,121 @@ +From f0217c42c9ab3d772e543f635ce628b9478f70b6 Mon Sep 17 00:00:00 2001 +From: Eric Anholt +Date: Tue, 1 Dec 2009 11:56:30 -0800 +Subject: drm/i915: Fix DDC on some systems by clearing BIOS GMBUS setup. + +From: Eric Anholt + +commit f0217c42c9ab3d772e543f635ce628b9478f70b6 upstream. + +This is a sync of a fix I made in the old UMS code. If the BIOS uses +the GMBUS and doesn't clear that setup, then our bit-banging I2C can +fail, leading to monitors not being detected. + +Signed-off-by: Eric Anholt +Cc: maximilian attems +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/i915_reg.h | 14 ++++++++++++++ + drivers/gpu/drm/i915/i915_suspend.c | 5 ++++- + drivers/gpu/drm/i915/intel_drv.h | 2 ++ + drivers/gpu/drm/i915/intel_i2c.c | 19 +++++++++++++++++++ + 4 files changed, 39 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/i915/i915_reg.h ++++ b/drivers/gpu/drm/i915/i915_reg.h +@@ -405,6 +405,13 @@ + # define GPIO_DATA_VAL_IN (1 << 12) + # define GPIO_DATA_PULLUP_DISABLE (1 << 13) + ++#define GMBUS0 0x5100 ++#define GMBUS1 0x5104 ++#define GMBUS2 0x5108 ++#define GMBUS3 0x510c ++#define GMBUS4 0x5110 ++#define GMBUS5 0x5120 ++ + /* + * Clock control & power management + */ +@@ -2153,6 +2160,13 @@ + #define PCH_GPIOE 0xc5020 + #define PCH_GPIOF 0xc5024 + ++#define PCH_GMBUS0 0xc5100 ++#define PCH_GMBUS1 0xc5104 ++#define PCH_GMBUS2 0xc5108 ++#define PCH_GMBUS3 0xc510c ++#define PCH_GMBUS4 0xc5110 ++#define PCH_GMBUS5 0xc5120 ++ + #define PCH_DPLL_A 0xc6014 + #define PCH_DPLL_B 0xc6018 + +--- a/drivers/gpu/drm/i915/i915_suspend.c ++++ b/drivers/gpu/drm/i915/i915_suspend.c +@@ -27,7 +27,7 @@ + #include "drmP.h" + #include "drm.h" + #include "i915_drm.h" +-#include "i915_drv.h" ++#include "intel_drv.h" + + static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe) + { +@@ -846,6 +846,9 @@ int i915_restore_state(struct drm_device + for (i = 0; i < 3; i++) + I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]); + ++ /* I2C state */ ++ intel_i2c_reset_gmbus(dev); ++ + return 0; + } + +--- a/drivers/gpu/drm/i915/intel_drv.h ++++ b/drivers/gpu/drm/i915/intel_drv.h +@@ -134,6 +134,8 @@ void intel_i2c_destroy(struct i2c_adapte + int intel_ddc_get_modes(struct intel_output *intel_output); + extern bool intel_ddc_probe(struct intel_output *intel_output); + void intel_i2c_quirk_set(struct drm_device *dev, bool enable); ++void intel_i2c_reset_gmbus(struct drm_device *dev); ++ + extern void intel_crt_init(struct drm_device *dev); + extern void intel_hdmi_init(struct drm_device *dev, int sdvox_reg); + extern bool intel_sdvo_init(struct drm_device *dev, int output_device); +--- a/drivers/gpu/drm/i915/intel_i2c.c ++++ b/drivers/gpu/drm/i915/intel_i2c.c +@@ -118,6 +118,23 @@ static void set_data(void *data, int sta + udelay(I2C_RISEFALL_TIME); /* wait for the line to change state */ + } + ++/* Clears the GMBUS setup. Our driver doesn't make use of the GMBUS I2C ++ * engine, but if the BIOS leaves it enabled, then that can break our use ++ * of the bit-banging I2C interfaces. This is notably the case with the ++ * Mac Mini in EFI mode. ++ */ ++void ++intel_i2c_reset_gmbus(struct drm_device *dev) ++{ ++ struct drm_i915_private *dev_priv = dev->dev_private; ++ ++ if (IS_IGDNG(dev)) { ++ I915_WRITE(PCH_GMBUS0, 0); ++ } else { ++ I915_WRITE(GMBUS0, 0); ++ } ++} ++ + /** + * intel_i2c_create - instantiate an Intel i2c bus using the specified GPIO reg + * @dev: DRM device +@@ -168,6 +185,8 @@ struct i2c_adapter *intel_i2c_create(str + if(i2c_bit_add_bus(&chan->adapter)) + goto out_free; + ++ intel_i2c_reset_gmbus(dev); ++ + /* JJJ: raise SCL and SDA? */ + intel_i2c_quirk_set(dev, true); + set_data(chan, 1); diff --git a/queue-2.6.32/drm-i915-fix-the-incorrect-dmi-string-for-samsung-sx20s-laptop.patch b/queue-2.6.32/drm-i915-fix-the-incorrect-dmi-string-for-samsung-sx20s-laptop.patch new file mode 100644 index 00000000000..51142a4451e --- /dev/null +++ b/queue-2.6.32/drm-i915-fix-the-incorrect-dmi-string-for-samsung-sx20s-laptop.patch @@ -0,0 +1,29 @@ +From f034b12dbb5749b11e9390e15e93ffa87ece8038 Mon Sep 17 00:00:00 2001 +From: Zhao Yakui +Date: Thu, 21 Jan 2010 15:20:18 +0800 +Subject: drm/i915: Fix the incorrect DMI string for Samsung SX20S laptop + +From: Zhao Yakui + +commit f034b12dbb5749b11e9390e15e93ffa87ece8038 upstream. + +Signed-off-by: Zhao Yakui +Reported-by: Philipp Kohlbecher +Signed-off-by: Eric Anholt +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/intel_lvds.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/i915/intel_lvds.c ++++ b/drivers/gpu/drm/i915/intel_lvds.c +@@ -611,7 +611,7 @@ static const struct dmi_system_id bad_li + { + .ident = "Samsung SX20S", + .matches = { +- DMI_MATCH(DMI_SYS_VENDOR, "Phoenix Technologies LTD"), ++ DMI_MATCH(DMI_SYS_VENDOR, "Samsung Electronics"), + DMI_MATCH(DMI_BOARD_NAME, "SX20S"), + }, + }, diff --git a/queue-2.6.32/hwmon-adt7462-wrong-adt7462_volt_count.patch b/queue-2.6.32/hwmon-adt7462-wrong-adt7462_volt_count.patch new file mode 100644 index 00000000000..4999ad2006b --- /dev/null +++ b/queue-2.6.32/hwmon-adt7462-wrong-adt7462_volt_count.patch @@ -0,0 +1,36 @@ +From 85f8d3e5faea8bd36c3e5196f8334f7db45e19b2 Mon Sep 17 00:00:00 2001 +From: Ray Copeland +Date: Fri, 5 Feb 2010 19:58:35 +0100 +Subject: hwmon: (adt7462) Wrong ADT7462_VOLT_COUNT + +From: Ray Copeland + +commit 85f8d3e5faea8bd36c3e5196f8334f7db45e19b2 upstream. + +The #define ADT7462_VOLT_COUNT is wrong, it should be 13 not 12. All the +for loops that use this as a limit count are of the typical form, "for +(n = 0; n < ADT7462_VOLT_COUNT; n++)", so to loop through all voltages +w/o missing the last one it is necessary for the count to be one greater +than it is. (Specifically, you will miss the +1.5V 3GPIO input with count += 12 vs. 13.) + +Signed-off-by: Ray Copeland +Acked-by: "Darrick J. Wong" +Signed-off-by: Jean Delvare +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/hwmon/adt7462.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/hwmon/adt7462.c ++++ b/drivers/hwmon/adt7462.c +@@ -182,7 +182,7 @@ I2C_CLIENT_INSMOD_1(adt7462); + * + * Some, but not all, of these voltages have low/high limits. + */ +-#define ADT7462_VOLT_COUNT 12 ++#define ADT7462_VOLT_COUNT 13 + + #define ADT7462_VENDOR 0x41 + #define ADT7462_DEVICE 0x62 diff --git a/queue-2.6.32/hwmon-lm78-request-i-o-ports-individually-for-probing.patch b/queue-2.6.32/hwmon-lm78-request-i-o-ports-individually-for-probing.patch new file mode 100644 index 00000000000..17d404772d5 --- /dev/null +++ b/queue-2.6.32/hwmon-lm78-request-i-o-ports-individually-for-probing.patch @@ -0,0 +1,66 @@ +From 197027e6ef830d60e10f76efc8d12bf3b6c35db5 Mon Sep 17 00:00:00 2001 +From: Jean Delvare +Date: Fri, 5 Feb 2010 19:58:36 +0100 +Subject: hwmon: (lm78) Request I/O ports individually for probing + +From: Jean Delvare + +commit 197027e6ef830d60e10f76efc8d12bf3b6c35db5 upstream. + +Different motherboards have different PNP declarations for LM78/LM79 +chips. Some declare the whole range of I/O ports (8 ports), some +declare only the useful ports (2 ports at offset 5) and some declare +fancy ranges, for example 4 ports at offset 4. To properly handle all +cases, request all ports individually for probing. After we have +determined that we really have an LM78 or LM79 chip, the useful port +range will be requested again, as a single block. + +This fixes the driver on the Olivetti M3000 DT 540, at least. + +Signed-off-by: Jean Delvare +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/hwmon/lm78.c | 23 +++++++++++------------ + 1 file changed, 11 insertions(+), 12 deletions(-) + +--- a/drivers/hwmon/lm78.c ++++ b/drivers/hwmon/lm78.c +@@ -870,17 +870,16 @@ static struct lm78_data *lm78_update_dev + static int __init lm78_isa_found(unsigned short address) + { + int val, save, found = 0; ++ int port; + +- /* We have to request the region in two parts because some +- boards declare base+4 to base+7 as a PNP device */ +- if (!request_region(address, 4, "lm78")) { +- pr_debug("lm78: Failed to request low part of region\n"); +- return 0; +- } +- if (!request_region(address + 4, 4, "lm78")) { +- pr_debug("lm78: Failed to request high part of region\n"); +- release_region(address, 4); +- return 0; ++ /* Some boards declare base+0 to base+7 as a PNP device, some base+4 ++ * to base+7 and some base+5 to base+6. So we better request each port ++ * individually for the probing phase. */ ++ for (port = address; port < address + LM78_EXTENT; port++) { ++ if (!request_region(port, 1, "lm78")) { ++ pr_debug("lm78: Failed to request port 0x%x\n", port); ++ goto release; ++ } + } + + #define REALLY_SLOW_IO +@@ -944,8 +943,8 @@ static int __init lm78_isa_found(unsigne + val & 0x80 ? "LM79" : "LM78", (int)address); + + release: +- release_region(address + 4, 4); +- release_region(address, 4); ++ for (port--; port >= address; port--) ++ release_region(port, 1); + return found; + } + diff --git a/queue-2.6.32/hwmon-w83781d-request-i-o-ports-individually-for-probing.patch b/queue-2.6.32/hwmon-w83781d-request-i-o-ports-individually-for-probing.patch new file mode 100644 index 00000000000..99004e51435 --- /dev/null +++ b/queue-2.6.32/hwmon-w83781d-request-i-o-ports-individually-for-probing.patch @@ -0,0 +1,69 @@ +From b0bcdd3cd0adb85a7686b396ba50493871b1135c Mon Sep 17 00:00:00 2001 +From: Jean Delvare +Date: Fri, 5 Feb 2010 19:58:36 +0100 +Subject: hwmon: (w83781d) Request I/O ports individually for probing + +From: Jean Delvare + +commit b0bcdd3cd0adb85a7686b396ba50493871b1135c upstream. + +Different motherboards have different PNP declarations for +W83781D/W83782D chips. Some declare the whole range of I/O ports (8 +ports), some declare only the useful ports (2 ports at offset 5) and +some declare fancy ranges, for example 4 ports at offset 4. To +properly handle all cases, request all ports individually for probing. +After we have determined that we really have a W83781D or W83782D +chip, the useful port range will be requested again, as a single +block. + +I did not see a board which needs this yet, but I know of one for lm78 +driver and I'd like to keep the logic of these two drivers in sync. + +Signed-off-by: Jean Delvare +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/hwmon/w83781d.c | 24 ++++++++++++------------ + 1 file changed, 12 insertions(+), 12 deletions(-) + +--- a/drivers/hwmon/w83781d.c ++++ b/drivers/hwmon/w83781d.c +@@ -1818,17 +1818,17 @@ static int __init + w83781d_isa_found(unsigned short address) + { + int val, save, found = 0; ++ int port; + +- /* We have to request the region in two parts because some +- boards declare base+4 to base+7 as a PNP device */ +- if (!request_region(address, 4, "w83781d")) { +- pr_debug("w83781d: Failed to request low part of region\n"); +- return 0; +- } +- if (!request_region(address + 4, 4, "w83781d")) { +- pr_debug("w83781d: Failed to request high part of region\n"); +- release_region(address, 4); +- return 0; ++ /* Some boards declare base+0 to base+7 as a PNP device, some base+4 ++ * to base+7 and some base+5 to base+6. So we better request each port ++ * individually for the probing phase. */ ++ for (port = address; port < address + W83781D_EXTENT; port++) { ++ if (!request_region(port, 1, "w83781d")) { ++ pr_debug("w83781d: Failed to request port 0x%x\n", ++ port); ++ goto release; ++ } + } + + #define REALLY_SLOW_IO +@@ -1902,8 +1902,8 @@ w83781d_isa_found(unsigned short address + val == 0x30 ? "W83782D" : "W83781D", (int)address); + + release: +- release_region(address + 4, 4); +- release_region(address, 4); ++ for (port--; port >= address; port--) ++ release_region(port, 1); + return found; + } + diff --git a/queue-2.6.32/i2c-tiny-usb-fix-on-big-endian-systems.patch b/queue-2.6.32/i2c-tiny-usb-fix-on-big-endian-systems.patch new file mode 100644 index 00000000000..312053bcd0e --- /dev/null +++ b/queue-2.6.32/i2c-tiny-usb-fix-on-big-endian-systems.patch @@ -0,0 +1,78 @@ +From 1c010ff8912cbc08d80e865aab9c32b6b00c527d Mon Sep 17 00:00:00 2001 +From: Jean Delvare +Date: Fri, 5 Feb 2010 17:48:13 +0100 +Subject: i2c-tiny-usb: Fix on big-endian systems + +From: Jean Delvare + +commit 1c010ff8912cbc08d80e865aab9c32b6b00c527d upstream. + +The functionality bit vector is always returned as a little-endian +32-bit number by the device, so it must be byte-swapped to the host +endianness. + +On the other hand, the delay value is handled by the USB stack, so no +byte swapping is needed on our side. + +This fixes bug #15105: +http://bugzilla.kernel.org/show_bug.cgi?id=15105 + +Reported-by: Jens Richter +Signed-off-by: Jean Delvare +Tested-by: Jens Richter +Cc: Till Harbaum +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/i2c/busses/i2c-tiny-usb.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +--- a/drivers/i2c/busses/i2c-tiny-usb.c ++++ b/drivers/i2c/busses/i2c-tiny-usb.c +@@ -13,6 +13,7 @@ + #include + #include + #include ++#include + + /* include interfaces to usb layer */ + #include +@@ -31,8 +32,8 @@ + #define CMD_I2C_IO_END (1<<1) + + /* i2c bit delay, default is 10us -> 100kHz */ +-static int delay = 10; +-module_param(delay, int, 0); ++static unsigned short delay = 10; ++module_param(delay, ushort, 0); + MODULE_PARM_DESC(delay, "bit delay in microseconds, " + "e.g. 10 for 100kHz (default is 100kHz)"); + +@@ -109,7 +110,7 @@ static int usb_xfer(struct i2c_adapter * + + static u32 usb_func(struct i2c_adapter *adapter) + { +- u32 func; ++ __le32 func; + + /* get functionality from adapter */ + if (usb_read(adapter, CMD_GET_FUNC, 0, 0, &func, sizeof(func)) != +@@ -118,7 +119,7 @@ static u32 usb_func(struct i2c_adapter * + return 0; + } + +- return func; ++ return le32_to_cpu(func); + } + + /* This is the actual algorithm we define */ +@@ -216,8 +217,7 @@ static int i2c_tiny_usb_probe(struct usb + "i2c-tiny-usb at bus %03d device %03d", + dev->usb_dev->bus->busnum, dev->usb_dev->devnum); + +- if (usb_write(&dev->adapter, CMD_SET_DELAY, +- cpu_to_le16(delay), 0, NULL, 0) != 0) { ++ if (usb_write(&dev->adapter, CMD_SET_DELAY, delay, 0, NULL, 0) != 0) { + dev_err(&dev->adapter.dev, + "failure setting delay to %dus\n", delay); + retval = -EIO; diff --git a/queue-2.6.32/series b/queue-2.6.32/series index 277fdc08072..317cda1f293 100644 --- a/queue-2.6.32/series +++ b/queue-2.6.32/series @@ -3,3 +3,16 @@ futex_lock_pi-key-refcnt-fix.patch futex-handle-user-space-corruption-gracefully.patch futex-handle-futex-value-corruption-gracefully.patch fix-race-in-tty_fasync-properly.patch +hwmon-w83781d-request-i-o-ports-individually-for-probing.patch +hwmon-lm78-request-i-o-ports-individually-for-probing.patch +hwmon-adt7462-wrong-adt7462_volt_count.patch +alsa-ctxfi-fix-ptp-address-initialization.patch +drm-i915-disable-hotplug-detect-before-ironlake-crt-detect.patch +drm-i915-enable-self-refresh-on-965.patch +drm-i915-disable-sr-when-more-than-one-pipe-is-enabled.patch +drm-i915-fix-ddc-on-some-systems-by-clearing-bios-gmbus-setup.patch +drm-i915-add-hp-nx9020-samsungsx20s-to-acpi-lid-quirk-list.patch +drm-i915-fix-the-incorrect-dmi-string-for-samsung-sx20s-laptop.patch +drm-i915-add-malata-pc-81005-to-acpi-lid-quirk-list.patch +usb-r8a66597-hcd-flush-the-d-cache-for-the-pipe-in-transfer-buffers.patch +i2c-tiny-usb-fix-on-big-endian-systems.patch diff --git a/queue-2.6.32/usb-r8a66597-hcd-flush-the-d-cache-for-the-pipe-in-transfer-buffers.patch b/queue-2.6.32/usb-r8a66597-hcd-flush-the-d-cache-for-the-pipe-in-transfer-buffers.patch new file mode 100644 index 00000000000..80b840f6d58 --- /dev/null +++ b/queue-2.6.32/usb-r8a66597-hcd-flush-the-d-cache-for-the-pipe-in-transfer-buffers.patch @@ -0,0 +1,104 @@ +From 2717568e7c44fe7dc3f4f52ea823811cfeede2b5 Mon Sep 17 00:00:00 2001 +From: Paul Mundt +Date: Thu, 4 Feb 2010 06:57:58 +0000 +Subject: usb: r8a66597-hcd: Flush the D-cache for the pipe-in transfer buffers. + +From: Paul Mundt + +commit 2717568e7c44fe7dc3f4f52ea823811cfeede2b5 upstream. + +This implements the same D-cache flushing logic for r8a66597-hcd as +Catalin's isp1760 (http://patchwork.kernel.org/patch/76391/) change, +with the same note applying here as well: + + When the HDC driver writes the data to the transfer buffers it + pollutes the D-cache (unlike DMA drivers where the device writes + the data). If the corresponding pages get mapped into user space, + there are no additional cache flushing operations performed and + this causes random user space faults on architectures with + separate I and D caches (Harvard) or those with aliasing D-cache. + +This fixes up crashes during USB boot on SH7724 and others: + + http://marc.info/?l=linux-sh&m=126439837308912&w=2 + +Reported-by: Goda Yusuke +Tested-by: Goda Yusuke +Signed-off-by: Paul Mundt +Acked-by: Yoshihiro Shimoda +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/usb/host/r8a66597-hcd.c | 39 ++++++++++++++++++++++++++------------- + 1 file changed, 26 insertions(+), 13 deletions(-) + +--- a/drivers/usb/host/r8a66597-hcd.c ++++ b/drivers/usb/host/r8a66597-hcd.c +@@ -35,7 +35,9 @@ + #include + #include + #include ++#include + #include ++#include + + #include "../core/hcd.h" + #include "r8a66597.h" +@@ -820,6 +822,26 @@ static void enable_r8a66597_pipe(struct + enable_r8a66597_pipe_dma(r8a66597, dev, pipe, urb); + } + ++static void r8a66597_urb_done(struct r8a66597 *r8a66597, struct urb *urb, ++ int status) ++__releases(r8a66597->lock) ++__acquires(r8a66597->lock) ++{ ++ if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) { ++ void *ptr; ++ ++ for (ptr = urb->transfer_buffer; ++ ptr < urb->transfer_buffer + urb->transfer_buffer_length; ++ ptr += PAGE_SIZE) ++ flush_dcache_page(virt_to_page(ptr)); ++ } ++ ++ usb_hcd_unlink_urb_from_ep(r8a66597_to_hcd(r8a66597), urb); ++ spin_unlock(&r8a66597->lock); ++ usb_hcd_giveback_urb(r8a66597_to_hcd(r8a66597), urb, status); ++ spin_lock(&r8a66597->lock); ++} ++ + /* this function must be called with interrupt disabled */ + static void force_dequeue(struct r8a66597 *r8a66597, u16 pipenum, u16 address) + { +@@ -840,15 +862,9 @@ static void force_dequeue(struct r8a6659 + list_del(&td->queue); + kfree(td); + +- if (urb) { +- usb_hcd_unlink_urb_from_ep(r8a66597_to_hcd(r8a66597), +- urb); +- +- spin_unlock(&r8a66597->lock); +- usb_hcd_giveback_urb(r8a66597_to_hcd(r8a66597), urb, +- -ENODEV); +- spin_lock(&r8a66597->lock); +- } ++ if (urb) ++ r8a66597_urb_done(r8a66597, urb, -ENODEV); ++ + break; + } + } +@@ -1285,10 +1301,7 @@ __releases(r8a66597->lock) __acquires(r8 + if (usb_pipeisoc(urb->pipe)) + urb->start_frame = r8a66597_get_frame(hcd); + +- usb_hcd_unlink_urb_from_ep(r8a66597_to_hcd(r8a66597), urb); +- spin_unlock(&r8a66597->lock); +- usb_hcd_giveback_urb(hcd, urb, status); +- spin_lock(&r8a66597->lock); ++ r8a66597_urb_done(r8a66597, urb, status); + } + + if (restart) {