From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Date: Thu, 25 Aug 2022 10:50:10 +0000 (+0200)
Subject: 4.9-stable patches
X-Git-Tag: v5.10.140~55
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=4ebc4dff85e8ef0203a86033b3e51d1387c9cced;p=thirdparty%2Fkernel%2Fstable-queue.git

4.9-stable patches

added patches:
	parisc-fix-exception-handler-for-fldw-and-fstw-instructions.patch
---

diff --git a/queue-4.9/parisc-fix-exception-handler-for-fldw-and-fstw-instructions.patch b/queue-4.9/parisc-fix-exception-handler-for-fldw-and-fstw-instructions.patch
new file mode 100644
index 00000000000..50d28aa5a41
--- /dev/null
+++ b/queue-4.9/parisc-fix-exception-handler-for-fldw-and-fstw-instructions.patch
@@ -0,0 +1,49 @@
+From 7ae1f5508d9a33fd58ed3059bd2d569961e3b8bd Mon Sep 17 00:00:00 2001
+From: Helge Deller <deller@gmx.de>
+Date: Sat, 20 Aug 2022 17:59:17 +0200
+Subject: parisc: Fix exception handler for fldw and fstw instructions
+
+From: Helge Deller <deller@gmx.de>
+
+commit 7ae1f5508d9a33fd58ed3059bd2d569961e3b8bd upstream.
+
+The exception handler is broken for unaligned memory acceses with fldw
+and fstw instructions, because it trashes or uses randomly some other
+floating point register than the one specified in the instruction word
+on loads and stores.
+
+The instruction "fldw 0(addr),%fr22L" (and the other fldw/fstw
+instructions) encode the target register (%fr22) in the rightmost 5 bits
+of the instruction word. The 7th rightmost bit of the instruction word
+defines if the left or right half of %fr22 should be used.
+
+While processing unaligned address accesses, the FR3() define is used to
+extract the offset into the local floating-point register set.  But the
+calculation in FR3() was buggy, so that for example instead of %fr22,
+register %fr12 [((22 * 2) & 0x1f) = 12] was used.
+
+This bug has been since forever in the parisc kernel and I wonder why it
+wasn't detected earlier. Interestingly I noticed this bug just because
+the libime debian package failed to build on *native* hardware, while it
+successfully built in qemu.
+
+This patch corrects the bitshift and masking calculation in FR3().
+
+Signed-off-by: Helge Deller <deller@gmx.de>
+Cc: <stable@vger.kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/parisc/kernel/unaligned.c |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/parisc/kernel/unaligned.c
++++ b/arch/parisc/kernel/unaligned.c
+@@ -120,7 +120,7 @@
+ #define R1(i) (((i)>>21)&0x1f)
+ #define R2(i) (((i)>>16)&0x1f)
+ #define R3(i) ((i)&0x1f)
+-#define FR3(i) ((((i)<<1)&0x1f)|(((i)>>6)&1))
++#define FR3(i) ((((i)&0x1f)<<1)|(((i)>>6)&1))
+ #define IM(i,n) (((i)>>1&((1<<(n-1))-1))|((i)&1?((0-1L)<<(n-1)):0))
+ #define IM5_2(i) IM((i)>>16,5)
+ #define IM5_3(i) IM((i),5)
diff --git a/queue-4.9/series b/queue-4.9/series
new file mode 100644
index 00000000000..68cd2e6f2e9
--- /dev/null
+++ b/queue-4.9/series
@@ -0,0 +1 @@
+parisc-fix-exception-handler-for-fldw-and-fstw-instructions.patch