From: Richard Henderson Date: Tue, 15 May 2018 13:58:43 +0000 (+0100) Subject: target/arm: Implement FMOV (general) for fp16 X-Git-Tag: v2.12.1~32 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=4ec6a17a04428f1a126216622b7f89107a185b50;p=thirdparty%2Fqemu.git target/arm: Implement FMOV (general) for fp16 Adding the fp16 moves to/from general registers. Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson Tested-by: Alex Bennée Message-id: 20180512003217.9105-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell (cherry picked from commit 68130236e30a1ec64363f4915349feee181bfbc1) Signed-off-by: Michael Roth --- diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 639cd95772c..b05f9bfe91d 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5457,6 +5457,15 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof) tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd)); clear_vec_high(s, true, rd); break; + case 3: + /* 16 bit */ + tmp = tcg_temp_new_i64(); + tcg_gen_ext16u_i64(tmp, tcg_rn); + write_fp_dreg(s, rd, tmp); + tcg_temp_free_i64(tmp); + break; + default: + g_assert_not_reached(); } } else { TCGv_i64 tcg_rd = cpu_reg(s, rd); @@ -5474,6 +5483,12 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof) /* 64 bits from top half */ tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn)); break; + case 3: + /* 16 bit */ + tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16)); + break; + default: + g_assert_not_reached(); } } } @@ -5513,6 +5528,12 @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn) case 0xa: /* 64 bit */ case 0xd: /* 64 bit to top half of quad */ break; + case 0x6: /* 16-bit float, 32-bit int */ + case 0xe: /* 16-bit float, 64-bit int */ + if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + break; + } + /* fallthru */ default: /* all other sf/type/rmode combinations are invalid */ unallocated_encoding(s);