From: Derek Basehore Date: Tue, 13 Mar 2018 20:37:19 +0000 (-0700) Subject: clk: rockchip: Add 1.6GHz PLL rate for rk3399 X-Git-Tag: v4.17-rc1~18^2~2^4~1^2 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=4ee3fd4abeca30d530fe67972f1964f7454259d6;p=thirdparty%2Fkernel%2Flinux.git clk: rockchip: Add 1.6GHz PLL rate for rk3399 We need this rate to generate 100, 200, and 228.57MHz from the same PLL. 228.57MHz is useful for a pixel clock when the VPLL is used for an external display. Signed-off-by: Derek Basehore Reviewed-by: Douglas Anderson Signed-off-by: Heiko Stuebner --- diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index 6847120b61cde..3e57c6eef93db 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -57,6 +57,7 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = { RK3036_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0), RK3036_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0), RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), + RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0), RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),