From: Nicholas Piggin Date: Mon, 15 May 2023 09:26:50 +0000 (+1000) Subject: target/ppc: Alignment faults do not set DSISR in ISA v3.0 onward X-Git-Tag: v8.1.0-rc0~89^2~7 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=4ee5d2817ff18d10be887853d5e966247f0a0c30;p=thirdparty%2Fqemu.git target/ppc: Alignment faults do not set DSISR in ISA v3.0 onward This optional behavior was removed from the ISA in v3.0, see Summary of Changes preface: Data Storage Interrupt Status Register for Alignment Interrupt: Simplifies the Alignment interrupt by remov- ing the Data Storage Interrupt Status Register (DSISR) from the set of registers modified by the Alignment interrupt. Reviewed-by: Fabiano Rosas Signed-off-by: Nicholas Piggin Message-Id: <20230515092655.171206-5-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza --- diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 199328f4b6a..fea92215013 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1431,13 +1431,16 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp) break; } case POWERPC_EXCP_ALIGN: /* Alignment exception */ - /* Get rS/rD and rA from faulting opcode */ - /* - * Note: the opcode fields will not be set properly for a - * direct store load/store, but nobody cares as nobody - * actually uses direct store segments. - */ - env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16; + /* Optional DSISR update was removed from ISA v3.0 */ + if (!(env->insns_flags2 & PPC2_ISA300)) { + /* Get rS/rD and rA from faulting opcode */ + /* + * Note: the opcode fields will not be set properly for a + * direct store load/store, but nobody cares as nobody + * actually uses direct store segments. + */ + env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16; + } break; case POWERPC_EXCP_PROGRAM: /* Program exception */ switch (env->error_code & ~0xF) {