From: Jakub Czapiga Date: Fri, 19 Sep 2025 18:15:47 +0000 (+0000) Subject: mtd: spi-nor: core: Check read CR support X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=5008c3ec3f891456e74f8dab882fcd5bc515d327;p=thirdparty%2Flinux.git mtd: spi-nor: core: Check read CR support Some SPI controllers like Intel's one on the PCI bus do not support opcode 35h. This opcode is used to read the Configuration Register on SPI-NOR chips that have 16-bit Status Register configured regardless of the controller support for it. Adding a check call in the setup step allows disabling use of the 35h opcode and falling back to the manual Status Registers management. Before: openat(AT_FDCWD, "/dev/mtd0", O_RDWR) = 4 ioctl(4, MIXER_WRITE(6) or MEMUNLOCK, {start=0, length=0x2000000}) = -1 EOPNOTSUPP After: openat(AT_FDCWD, "/dev/mtd0", O_RDWR) = 4 ioctl(4, MIXER_WRITE(6) or MEMUNLOCK, {start=0, length=0x2000000}) = 0 ioctl(4, MIXER_WRITE(5) or MEMLOCK, {start=0x1800000, length=0x800000}) = 0 Suggested-by: Adeel Arshad Signed-off-by: Jakub Czapiga Reviewed-by: Pratyush Yadav Signed-off-by: Pratyush Yadav --- diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 20ea80450f222..d3f8a78efd3bf 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2459,6 +2459,16 @@ spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32 *hwcaps) ¶ms->page_programs[ppidx])) *hwcaps &= ~BIT(cap); } + + /* Some SPI controllers might not support CR read opcode. */ + if (!(nor->flags & SNOR_F_NO_READ_CR)) { + struct spi_mem_op op = SPI_NOR_RDCR_OP(nor->bouncebuf); + + spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); + + if (spi_nor_spimem_check_op(nor, &op)) + nor->flags |= SNOR_F_NO_READ_CR; + } } /**