From: Greg Kroah-Hartman Date: Sat, 30 Mar 2024 09:20:40 +0000 (+0100) Subject: 5.15-stable patches X-Git-Tag: v6.7.12~124 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=510aedd69bdee5ad61a59c2b0c56c8a04842ab91;p=thirdparty%2Fkernel%2Fstable-queue.git 5.15-stable patches added patches: mm-migrate-set-swap-entry-values-of-thp-tail-pages-properly.patch serial-sc16is7xx-convert-from-_raw_-to-_noinc_-regmap-functions-for-fifo.patch --- diff --git a/queue-5.15/mm-migrate-set-swap-entry-values-of-thp-tail-pages-properly.patch b/queue-5.15/mm-migrate-set-swap-entry-values-of-thp-tail-pages-properly.patch new file mode 100644 index 00000000000..be43d2fd47f --- /dev/null +++ b/queue-5.15/mm-migrate-set-swap-entry-values-of-thp-tail-pages-properly.patch @@ -0,0 +1,55 @@ +From stable+bounces-27000-greg=kroah.com@vger.kernel.org Wed Mar 6 16:52:16 2024 +From: Zi Yan +Date: Wed, 6 Mar 2024 10:51:57 -0500 +Subject: mm/migrate: set swap entry values of THP tail pages properly. +To: gregkh@linuxfoundation.org, stable@vger.kernel.org +Cc: Zi Yan , linux-mm@kvack.org, Charan Teja Kalla , "Matthew Wilcox (Oracle)" , David Hildenbrand , Andrew Morton , Huang Ying , Naoya Horiguchi +Message-ID: <20240306155157.118343-1-zi.yan@sent.com> + +From: Zi Yan + +The tail pages in a THP can have swap entry information stored in their +private field. When migrating to a new page, all tail pages of the new +page need to update ->private to avoid future data corruption. + +This fix is stable-only, since after commit 07e09c483cbe ("mm/huge_memory: +work on folio->swap instead of page->private when splitting folio"), +subpages of a swapcached THP no longer requires the maintenance. + +Adding THPs to the swapcache was introduced in commit +38d8b4e6bdc87 ("mm, THP, swap: delay splitting THP during swap out"), +where each subpage of a THP added to the swapcache had its own swapcache +entry and required the ->private field to point to the correct swapcache +entry. Later, when THP migration functionality was implemented in commit +616b8371539a6 ("mm: thp: enable thp migration in generic path"), +it initially did not handle the subpages of swapcached THPs, failing to +update their ->private fields or replace the subpage pointers in the +swapcache. Subsequently, commit e71769ae5260 ("mm: enable thp migration +for shmem thp") addressed the swapcache update aspect. This patch fixes +the update of subpage ->private fields. + +Closes: https://lore.kernel.org/linux-mm/1707814102-22682-1-git-send-email-quic_charante@quicinc.com/ +Fixes: 616b8371539a ("mm: thp: enable thp migration in generic path") +Signed-off-by: Zi Yan +Acked-by: David Hildenbrand +Signed-off-by: Greg Kroah-Hartman +--- + mm/migrate.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +--- a/mm/migrate.c ++++ b/mm/migrate.c +@@ -424,8 +424,12 @@ int migrate_page_move_mapping(struct add + if (PageSwapBacked(page)) { + __SetPageSwapBacked(newpage); + if (PageSwapCache(page)) { ++ int i; ++ + SetPageSwapCache(newpage); +- set_page_private(newpage, page_private(page)); ++ for (i = 0; i < (1 << compound_order(page)); i++) ++ set_page_private(newpage + i, ++ page_private(page + i)); + } + } else { + VM_BUG_ON_PAGE(PageSwapCache(page), page); diff --git a/queue-5.15/serial-sc16is7xx-convert-from-_raw_-to-_noinc_-regmap-functions-for-fifo.patch b/queue-5.15/serial-sc16is7xx-convert-from-_raw_-to-_noinc_-regmap-functions-for-fifo.patch new file mode 100644 index 00000000000..7b8c92588e2 --- /dev/null +++ b/queue-5.15/serial-sc16is7xx-convert-from-_raw_-to-_noinc_-regmap-functions-for-fifo.patch @@ -0,0 +1,83 @@ +From dbf4ab821804df071c8b566d9813083125e6d97b Mon Sep 17 00:00:00 2001 +From: Hugo Villeneuve +Date: Mon, 11 Dec 2023 12:13:52 -0500 +Subject: serial: sc16is7xx: convert from _raw_ to _noinc_ regmap functions for FIFO + +From: Hugo Villeneuve + +commit dbf4ab821804df071c8b566d9813083125e6d97b upstream. + +The SC16IS7XX IC supports a burst mode to access the FIFOs where the +initial register address is sent ($00), followed by all the FIFO data +without having to resend the register address each time. In this mode, the +IC doesn't increment the register address for each R/W byte. + +The regmap_raw_read() and regmap_raw_write() are functions which can +perform IO over multiple registers. They are currently used to read/write +from/to the FIFO, and although they operate correctly in this burst mode on +the SPI bus, they would corrupt the regmap cache if it was not disabled +manually. The reason is that when the R/W size is more than 1 byte, these +functions assume that the register address is incremented and handle the +cache accordingly. + +Convert FIFO R/W functions to use the regmap _noinc_ versions in order to +remove the manual cache control which was a workaround when using the +_raw_ versions. FIFO registers are properly declared as volatile so +cache will not be used/updated for FIFO accesses. + +Fixes: dfeae619d781 ("serial: sc16is7xx") +Cc: +Signed-off-by: Hugo Villeneuve +Link: https://lore.kernel.org/r/20231211171353.2901416-6-hugo@hugovil.com +Cc: Hugo Villeneuve +Signed-off-by: GONG, Ruiqi +Signed-off-by: Greg Kroah-Hartman +--- + drivers/tty/serial/sc16is7xx.c | 15 +++++++++------ + 1 file changed, 9 insertions(+), 6 deletions(-) + +--- a/drivers/tty/serial/sc16is7xx.c ++++ b/drivers/tty/serial/sc16is7xx.c +@@ -376,9 +376,7 @@ static void sc16is7xx_fifo_read(struct u + const u8 line = sc16is7xx_line(port); + u8 addr = (SC16IS7XX_RHR_REG << SC16IS7XX_REG_SHIFT) | line; + +- regcache_cache_bypass(s->regmap, true); +- regmap_raw_read(s->regmap, addr, s->buf, rxlen); +- regcache_cache_bypass(s->regmap, false); ++ regmap_noinc_read(s->regmap, addr, s->buf, rxlen); + } + + static void sc16is7xx_fifo_write(struct uart_port *port, u8 to_send) +@@ -394,9 +392,7 @@ static void sc16is7xx_fifo_write(struct + if (unlikely(!to_send)) + return; + +- regcache_cache_bypass(s->regmap, true); +- regmap_raw_write(s->regmap, addr, s->buf, to_send); +- regcache_cache_bypass(s->regmap, false); ++ regmap_noinc_write(s->regmap, addr, s->buf, to_send); + } + + static void sc16is7xx_port_update(struct uart_port *port, u8 reg, +@@ -489,6 +485,11 @@ static bool sc16is7xx_regmap_precious(st + return false; + } + ++static bool sc16is7xx_regmap_noinc(struct device *dev, unsigned int reg) ++{ ++ return reg == SC16IS7XX_RHR_REG; ++} ++ + static int sc16is7xx_set_baud(struct uart_port *port, int baud) + { + struct sc16is7xx_port *s = dev_get_drvdata(port->dev); +@@ -1439,6 +1440,8 @@ static struct regmap_config regcfg = { + .cache_type = REGCACHE_RBTREE, + .volatile_reg = sc16is7xx_regmap_volatile, + .precious_reg = sc16is7xx_regmap_precious, ++ .writeable_noinc_reg = sc16is7xx_regmap_noinc, ++ .readable_noinc_reg = sc16is7xx_regmap_noinc, + }; + + #ifdef CONFIG_SERIAL_SC16IS7XX_SPI diff --git a/queue-5.15/series b/queue-5.15/series index b7cdf1ccd3c..6542548fded 100644 --- a/queue-5.15/series +++ b/queue-5.15/series @@ -564,3 +564,5 @@ vfio-introduce-interface-to-flush-virqfd-inject-workqueue.patch vfio-pci-create-persistent-intx-handler.patch vfio-platform-create-persistent-irq-handlers.patch vfio-fsl-mc-block-calling-interrupt-handler-without-trigger.patch +serial-sc16is7xx-convert-from-_raw_-to-_noinc_-regmap-functions-for-fifo.patch +mm-migrate-set-swap-entry-values-of-thp-tail-pages-properly.patch