From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Date: Thu, 26 Jul 2018 14:50:38 +0000 (+0200)
Subject: 4.4-stable patches
X-Git-Tag: v3.18.117~17
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=51607978a65ef239dcb0df6c794106842e08db34;p=thirdparty%2Fkernel%2Fstable-queue.git

4.4-stable patches

added patches:
	mips-ath79-fix-register-address-in-ath79_ddr_wb_flush.patch
---

diff --git a/queue-4.4/mips-ath79-fix-register-address-in-ath79_ddr_wb_flush.patch b/queue-4.4/mips-ath79-fix-register-address-in-ath79_ddr_wb_flush.patch
new file mode 100644
index 00000000000..60284a970ba
--- /dev/null
+++ b/queue-4.4/mips-ath79-fix-register-address-in-ath79_ddr_wb_flush.patch
@@ -0,0 +1,39 @@
+From bc88ad2efd11f29e00a4fd60fcd1887abfe76833 Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@nbd.name>
+Date: Fri, 20 Jul 2018 13:58:21 +0200
+Subject: MIPS: ath79: fix register address in ath79_ddr_wb_flush()
+
+From: Felix Fietkau <nbd@nbd.name>
+
+commit bc88ad2efd11f29e00a4fd60fcd1887abfe76833 upstream.
+
+ath79_ddr_wb_flush_base has the type void __iomem *, so register offsets
+need to be a multiple of 4 in order to access the intended register.
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+Signed-off-by: John Crispin <john@phrozen.org>
+Signed-off-by: Paul Burton <paul.burton@mips.com>
+Fixes: 24b0e3e84fbf ("MIPS: ath79: Improve the DDR controller interface")
+Patchwork: https://patchwork.linux-mips.org/patch/19912/
+Cc: Alban Bedel <albeu@free.fr>
+Cc: James Hogan <jhogan@kernel.org>
+Cc: Ralf Baechle <ralf@linux-mips.org>
+Cc: linux-mips@linux-mips.org
+Cc: stable@vger.kernel.org # 4.2+
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/mips/ath79/common.c |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/mips/ath79/common.c
++++ b/arch/mips/ath79/common.c
+@@ -58,7 +58,7 @@ EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init);
+ 
+ void ath79_ddr_wb_flush(u32 reg)
+ {
+-	void __iomem *flush_reg = ath79_ddr_wb_flush_base + reg;
++	void __iomem *flush_reg = ath79_ddr_wb_flush_base + (reg * 4);
+ 
+ 	/* Flush the DDR write buffer. */
+ 	__raw_writel(0x1, flush_reg);