From: Paolo Abeni Date: Tue, 28 Oct 2025 10:11:38 +0000 (+0100) Subject: Merge branch 'net-mlx5-add-balance-id-support-for-lag-multiplane-groups' X-Git-Tag: v6.19-rc1~170^2~299 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=51f322550b1b7660fb8be655d82a68e49fdd60f5;p=thirdparty%2Fkernel%2Flinux.git Merge branch 'net-mlx5-add-balance-id-support-for-lag-multiplane-groups' Tariq Toukan says: ==================== net/mlx5: Add balance ID support for LAG multiplane groups This series adds balance ID support for MLX5 LAG in multiplane configurations. See detailed description by Mark below [1]. [1] The problem: In complex multiplane LAG setups, we need finer control over LAG groups. Currently, devices with the same system image GUID are treated identically, but hardware now supports per-multiplane-group balance IDs that let us differentiate between them. On such systems image system guid isn't enough to decide which devices should be part of which LAG. The solution: Extend the system image GUID with a balance ID byte when the hardware supports it. This gives us the granularity we need without breaking existing deployments. What this series does: 1. Clean up some duplicate code while we're here 2. Rework the system image GUID infrastructure to handle variable lengths 3. Update PTP clock pairing to use the new approach 4. Restructure capability setting to make room for the new feature 5. Actually implement the balance ID support The key insight is in patch 5: we only append the balance ID when both capabilities are present, so older hardware and software continue to work exactly as before. For newer setups, you get the extra byte that enables per-multiplane-group load balancing. This has been tested with both old and new hardware configurations. ==================== Link: https://patch.msgid.link/1761211020-925651-1-git-send-email-tariqt@nvidia.com Signed-off-by: Paolo Abeni --- 51f322550b1b7660fb8be655d82a68e49fdd60f5