From: Geert Uytterhoeven Date: Fri, 21 Feb 2025 08:44:47 +0000 (+0100) Subject: clk: renesas: r7s9210: Distinguish clocks by clock type X-Git-Tag: v6.15-rc1~103^2~2^2^2~2 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=5288fe0e2e9d2c147e18c5ce4d03d17f34132dde;p=thirdparty%2Flinux.git clk: renesas: r7s9210: Distinguish clocks by clock type When registering a clock, its type should be devised from the clock's type member, not from its id member. Merge the two checks for the main clock, to improve readability. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/7e61ea78e9919148e73867088ccbc3509364952e.1740126560.git.geert+renesas@glider.be --- diff --git a/drivers/clk/renesas/r7s9210-cpg-mssr.c b/drivers/clk/renesas/r7s9210-cpg-mssr.c index a85227c248f31..e1812867a6da4 100644 --- a/drivers/clk/renesas/r7s9210-cpg-mssr.c +++ b/drivers/clk/renesas/r7s9210-cpg-mssr.c @@ -170,11 +170,12 @@ static struct clk * __init rza2_cpg_clk_register(struct device *dev, if (IS_ERR(parent)) return ERR_CAST(parent); - switch (core->id) { - case CLK_MAIN: + switch (core->type) { + case CLK_TYPE_RZA_MAIN: + r7s9210_update_clk_table(parent, base); break; - case CLK_PLL: + case CLK_TYPE_RZA_PLL: if (cpg_mode) mult = 44; /* Divider 1 is 1/2 */ else @@ -185,9 +186,6 @@ static struct clk * __init rza2_cpg_clk_register(struct device *dev, return ERR_PTR(-EINVAL); } - if (core->id == CLK_MAIN) - r7s9210_update_clk_table(parent, base); - return clk_register_fixed_factor(NULL, core->name, __clk_get_name(parent), 0, mult, div); }