From: Greg Kroah-Hartman Date: Sun, 6 Feb 2022 12:25:18 +0000 (+0100) Subject: 5.16-stable patches X-Git-Tag: v4.9.300~34 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=52bf0da88b21c165bd23367b114157b401dbd2ab;p=thirdparty%2Fkernel%2Fstable-queue.git 5.16-stable patches added patches: arm64-add-cortex-a510-cpu-part-definition.patch kvm-arm64-avoid-consuming-a-stale-esr-value-when-serror-occur.patch kvm-arm64-stop-handle_exit-from-handling-hvc-twice-when-an-serror-occurs.patch risc-v-kvm-make-cy-tm-and-ir-counters-accessible-in-vu-mode.patch --- diff --git a/queue-5.16/arm64-add-cortex-a510-cpu-part-definition.patch b/queue-5.16/arm64-add-cortex-a510-cpu-part-definition.patch new file mode 100644 index 00000000000..777ba3e3dff --- /dev/null +++ b/queue-5.16/arm64-add-cortex-a510-cpu-part-definition.patch @@ -0,0 +1,44 @@ +From 53960faf2b731dd2f9ed6e1334634b8ba6286850 Mon Sep 17 00:00:00 2001 +From: Anshuman Khandual +Date: Tue, 25 Jan 2022 19:50:31 +0530 +Subject: arm64: Add Cortex-A510 CPU part definition + +From: Anshuman Khandual + +commit 53960faf2b731dd2f9ed6e1334634b8ba6286850 upstream. + +Add the CPU Partnumbers for the new Arm designs. + +Cc: Catalin Marinas +Cc: Will Deacon +Cc: Suzuki Poulose +Cc: linux-arm-kernel@lists.infradead.org +Cc: linux-kernel@vger.kernel.org +Reviewed-by: Suzuki K Poulose +Acked-by: Catalin Marinas +Signed-off-by: Anshuman Khandual +Link: https://lore.kernel.org/r/1643120437-14352-2-git-send-email-anshuman.khandual@arm.com +Signed-off-by: Mathieu Poirier +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/include/asm/cputype.h | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -73,6 +73,7 @@ + #define ARM_CPU_PART_CORTEX_A76 0xD0B + #define ARM_CPU_PART_NEOVERSE_N1 0xD0C + #define ARM_CPU_PART_CORTEX_A77 0xD0D ++#define ARM_CPU_PART_CORTEX_A510 0xD46 + #define ARM_CPU_PART_CORTEX_A710 0xD47 + #define ARM_CPU_PART_NEOVERSE_N2 0xD49 + +@@ -115,6 +116,7 @@ + #define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76) + #define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1) + #define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77) ++#define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510) + #define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710) + #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) + #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) diff --git a/queue-5.16/kvm-arm64-avoid-consuming-a-stale-esr-value-when-serror-occur.patch b/queue-5.16/kvm-arm64-avoid-consuming-a-stale-esr-value-when-serror-occur.patch new file mode 100644 index 00000000000..46c07ec5b2c --- /dev/null +++ b/queue-5.16/kvm-arm64-avoid-consuming-a-stale-esr-value-when-serror-occur.patch @@ -0,0 +1,51 @@ +From 1c71dbc8a179d99dd9bb7e7fc1888db613cf85de Mon Sep 17 00:00:00 2001 +From: James Morse +Date: Thu, 27 Jan 2022 12:20:50 +0000 +Subject: KVM: arm64: Avoid consuming a stale esr value when SError occur + +From: James Morse + +commit 1c71dbc8a179d99dd9bb7e7fc1888db613cf85de upstream. + +When any exception other than an IRQ occurs, the CPU updates the ESR_EL2 +register with the exception syndrome. An SError may also become pending, +and will be synchronised by KVM. KVM notes the exception type, and whether +an SError was synchronised in exit_code. + +When an exception other than an IRQ occurs, fixup_guest_exit() updates +vcpu->arch.fault.esr_el2 from the hardware register. When an SError was +synchronised, the vcpu esr value is used to determine if the exception +was due to an HVC. If so, ELR_EL2 is moved back one instruction. This +is so that KVM can process the SError first, and re-execute the HVC if +the guest survives the SError. + +But if an IRQ synchronises an SError, the vcpu's esr value is stale. +If the previous non-IRQ exception was an HVC, KVM will corrupt ELR_EL2, +causing an unrelated guest instruction to be executed twice. + +Check ARM_EXCEPTION_CODE() before messing with ELR_EL2, IRQs don't +update this register so don't need to check. + +Fixes: defe21f49bc9 ("KVM: arm64: Move PC rollback on SError to HYP") +Cc: stable@vger.kernel.org +Reported-by: Steven Price +Signed-off-by: James Morse +Signed-off-by: Marc Zyngier +Link: https://lore.kernel.org/r/20220127122052.1584324-3-james.morse@arm.com +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/kvm/hyp/include/hyp/switch.h | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/arch/arm64/kvm/hyp/include/hyp/switch.h ++++ b/arch/arm64/kvm/hyp/include/hyp/switch.h +@@ -446,7 +446,8 @@ static inline bool fixup_guest_exit(stru + if (ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ) + vcpu->arch.fault.esr_el2 = read_sysreg_el2(SYS_ESR); + +- if (ARM_SERROR_PENDING(*exit_code)) { ++ if (ARM_SERROR_PENDING(*exit_code) && ++ ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ) { + u8 esr_ec = kvm_vcpu_trap_get_class(vcpu); + + /* diff --git a/queue-5.16/kvm-arm64-stop-handle_exit-from-handling-hvc-twice-when-an-serror-occurs.patch b/queue-5.16/kvm-arm64-stop-handle_exit-from-handling-hvc-twice-when-an-serror-occurs.patch new file mode 100644 index 00000000000..740c06d30b5 --- /dev/null +++ b/queue-5.16/kvm-arm64-stop-handle_exit-from-handling-hvc-twice-when-an-serror-occurs.patch @@ -0,0 +1,54 @@ +From 1229630af88620f6e3a621a1ebd1ca14d9340df7 Mon Sep 17 00:00:00 2001 +From: James Morse +Date: Thu, 27 Jan 2022 12:20:51 +0000 +Subject: KVM: arm64: Stop handle_exit() from handling HVC twice when an SError occurs + +From: James Morse + +commit 1229630af88620f6e3a621a1ebd1ca14d9340df7 upstream. + +Prior to commit defe21f49bc9 ("KVM: arm64: Move PC rollback on SError to +HYP"), when an SError is synchronised due to another exception, KVM +handles the SError first. If the guest survives, the instruction that +triggered the original exception is re-exectued to handle the first +exception. HVC is treated as a special case as the instruction wouldn't +normally be re-exectued, as its not a trap. + +Commit defe21f49bc9 didn't preserve the behaviour of the 'return 1' +that skips the rest of handle_exit(). + +Since commit defe21f49bc9, KVM will try to handle the SError and the +original exception at the same time. When the exception was an HVC, +fixup_guest_exit() has already rolled back ELR_EL2, meaning if the +guest has virtual SError masked, it will execute and handle the HVC +twice. + +Restore the original behaviour. + +Fixes: defe21f49bc9 ("KVM: arm64: Move PC rollback on SError to HYP") +Cc: stable@vger.kernel.org +Signed-off-by: James Morse +Signed-off-by: Marc Zyngier +Link: https://lore.kernel.org/r/20220127122052.1584324-4-james.morse@arm.com +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/kvm/handle_exit.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/arch/arm64/kvm/handle_exit.c ++++ b/arch/arm64/kvm/handle_exit.c +@@ -226,6 +226,14 @@ int handle_exit(struct kvm_vcpu *vcpu, i + { + struct kvm_run *run = vcpu->run; + ++ if (ARM_SERROR_PENDING(exception_index)) { ++ /* ++ * The SError is handled by handle_exit_early(). If the guest ++ * survives it will re-execute the original instruction. ++ */ ++ return 1; ++ } ++ + exception_index = ARM_EXCEPTION_CODE(exception_index); + + switch (exception_index) { diff --git a/queue-5.16/risc-v-kvm-make-cy-tm-and-ir-counters-accessible-in-vu-mode.patch b/queue-5.16/risc-v-kvm-make-cy-tm-and-ir-counters-accessible-in-vu-mode.patch new file mode 100644 index 00000000000..b02aa63f80b --- /dev/null +++ b/queue-5.16/risc-v-kvm-make-cy-tm-and-ir-counters-accessible-in-vu-mode.patch @@ -0,0 +1,46 @@ +From de1d7b6a51dab546160d252e47baa54adf104d4a Mon Sep 17 00:00:00 2001 +From: Mayuresh Chitale +Date: Mon, 31 Jan 2022 16:33:07 +0530 +Subject: RISC-V: KVM: make CY, TM, and IR counters accessible in VU mode + +From: Mayuresh Chitale + +commit de1d7b6a51dab546160d252e47baa54adf104d4a upstream. + +Those applications that run in VU mode and access the time CSR cause +a virtual instruction trap as Guest kernel currently does not +initialize the scounteren CSR. + +To fix this, we should make CY, TM, and IR counters accessibile +by default in VU mode (similar to OpenSBI). + +Fixes: a33c72faf2d73 ("RISC-V: KVM: Implement VCPU create, init and +destroy functions") +Cc: stable@vger.kernel.org +Signed-off-by: Mayuresh Chitale +Signed-off-by: Anup Patel +Signed-off-by: Greg Kroah-Hartman +--- + arch/riscv/kvm/vcpu.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/arch/riscv/kvm/vcpu.c ++++ b/arch/riscv/kvm/vcpu.c +@@ -74,6 +74,7 @@ int kvm_arch_vcpu_precreate(struct kvm * + int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) + { + struct kvm_cpu_context *cntx; ++ struct kvm_vcpu_csr *reset_csr = &vcpu->arch.guest_reset_csr; + + /* Mark this VCPU never ran */ + vcpu->arch.ran_atleast_once = false; +@@ -89,6 +90,9 @@ int kvm_arch_vcpu_create(struct kvm_vcpu + cntx->hstatus |= HSTATUS_SPVP; + cntx->hstatus |= HSTATUS_SPV; + ++ /* By default, make CY, TM, and IR counters accessible in VU mode */ ++ reset_csr->scounteren = 0x7; ++ + /* Setup VCPU timer */ + kvm_riscv_vcpu_timer_init(vcpu); + diff --git a/queue-5.16/series b/queue-5.16/series index 1088c3fa909..6be082997ce 100644 --- a/queue-5.16/series +++ b/queue-5.16/series @@ -41,3 +41,7 @@ revert-fbcon-disable-accelerated-scrolling.patch fbcon-add-option-to-enable-legacy-hardware-acceleration.patch mptcp-fix-msk-traversal-in-mptcp_nl_cmd_set_flags.patch revert-asoc-mediatek-check-for-error-clk-pointer.patch +risc-v-kvm-make-cy-tm-and-ir-counters-accessible-in-vu-mode.patch +kvm-arm64-avoid-consuming-a-stale-esr-value-when-serror-occur.patch +kvm-arm64-stop-handle_exit-from-handling-hvc-twice-when-an-serror-occurs.patch +arm64-add-cortex-a510-cpu-part-definition.patch