From: Peter Maydell Date: Mon, 24 Feb 2020 17:28:44 +0000 (+0000) Subject: target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0 X-Git-Tag: v5.0.0-rc0~66^2~4 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=54117b90ffd8a3977917971c3bd99bb5242710d9;p=thirdparty%2Fqemu.git target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0 We missed an instance of using FIELD_EX32 on a 64-bit ID register, in isar_feature_aa64_pmu_8_4(). Fix it. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20200224172846.13053-2-peter.maydell@linaro.org --- diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 05aa9711cd8..6013287f623 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3770,8 +3770,8 @@ static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id) static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id) { - return FIELD_EX32(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 && - FIELD_EX32(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; + return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 && + FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; } /*