From: Allen-KH Cheng Date: Fri, 1 Jul 2022 12:12:29 +0000 (+0800) Subject: remoteproc: mediatek: Enable cache for mt8186 SCP X-Git-Tag: v6.0-rc1~56^2~35 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=54439d20c027f17ff022e828cb0c05b25ee2d124;p=thirdparty%2Fkernel%2Flinux.git remoteproc: mediatek: Enable cache for mt8186 SCP This patch is for enabling cache in SCP. There is not enough space on the SRAM of SCP. We need to run programs in DRAM. The DRAM power and latency is much larger than SRAM, so cache is used to mitigate the negative effects for performance. We set SCP registers for cache size before loading SCP FW. (8KB+8KB) and also adjust ipi_buf_offset in SRAM from 0x7bdb0 to 0x3bdb0 for enabling cache. Signed-off-by: Allen-KH Cheng Tested-by: TingHan Shen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220701121229.22756-2-allen-kh.cheng@mediatek.com Signed-off-by: Mathieu Poirier --- diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index 47b2a40e1b4a3..5b2ad789e7206 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -401,6 +401,14 @@ static int mt8186_scp_before_load(struct mtk_scp *scp) writel(0x0, scp->reg_base + MT8186_SCP_L1_SRAM_PD_P1); writel(0x0, scp->reg_base + MT8186_SCP_L1_SRAM_PD_p2); + /* + * Set I-cache and D-cache size before loading SCP FW. + * SCP SRAM logical address may change when cache size setting differs. + */ + writel(MT8183_SCP_CACHE_CON_WAYEN | MT8183_SCP_CACHESIZE_8KB, + scp->reg_base + MT8183_SCP_CACHE_CON); + writel(MT8183_SCP_CACHESIZE_8KB, scp->reg_base + MT8183_SCP_DCACHE_CON); + return 0; } @@ -943,7 +951,7 @@ static const struct mtk_scp_of_data mt8186_of_data = { .scp_da_to_va = mt8183_scp_da_to_va, .host_to_scp_reg = MT8183_HOST_TO_SCP, .host_to_scp_int_bit = MT8183_HOST_IPC_INT_BIT, - .ipi_buf_offset = 0x7bdb0, + .ipi_buf_offset = 0x3bdb0, }; static const struct mtk_scp_of_data mt8192_of_data = {