From: Mark Brown Date: Mon, 4 Jul 2022 17:02:52 +0000 (+0100) Subject: arm64/sysreg: Convert DCZID_EL0 to automatic generation X-Git-Tag: v6.0-rc1~203^2~4^2~10 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=5589083d802b1f1434f9481f671eee5d985f5772;p=thirdparty%2Flinux.git arm64/sysreg: Convert DCZID_EL0 to automatic generation Convert DCZID_EL0 to automatic register generation as per DDI0487H.a, no functional change. Signed-off-by: Mark Brown Link: https://lore.kernel.org/r/20220704170302.2609529-19-broonie@kernel.org Signed-off-by: Will Deacon --- diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 234f9a3844de6..1a6a04b96dfa7 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -461,8 +461,6 @@ #define SMIDR_EL1_SMPS_SHIFT 15 #define SMIDR_EL1_AFFINITY_SHIFT 0 -#define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7) - #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0) #define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1) @@ -1081,9 +1079,6 @@ #define MVFR2_FPMISC_SHIFT 4 #define MVFR2_SIMDMISC_SHIFT 0 -#define DCZID_EL0_DZP_SHIFT 4 -#define DCZID_EL0_BS_SHIFT 0 - #define CPACR_EL1_FPEN_EL1EN (BIT(20)) /* enable EL1 access */ #define CPACR_EL1_FPEN_EL0EN (BIT(21)) /* enable EL0 access, if EL1EN set */ diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index a9f4c157c4be9..c286b62958eab 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -294,6 +294,12 @@ Res0 13:4 Field 3:0 IminLine EndSysreg +Sysreg DCZID_EL0 3 3 0 0 7 +Res0 63:5 +Field 4 DZP +Field 3:0 BS +EndSysreg + Sysreg SVCR 3 3 4 2 2 Res0 63:2 Field 1 ZA