From: Kewen Lin <linkw@linux.ibm.com>
Date: Wed, 11 May 2022 06:18:30 +0000 (-0500)
Subject: rs6000: Fix constraint v with rs6000_constraints[RS6000_CONSTRAINT_v]
X-Git-Tag: basepoints/gcc-14~6924
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=55aa130ef112c6f2c8ef85c218455464c6b29d60;p=thirdparty%2Fgcc.git

rs6000: Fix constraint v with rs6000_constraints[RS6000_CONSTRAINT_v]

Currently we hardcode ALTIVEC_REGS for register constraint v and
RS6000_CONSTRAINT_v looks confusing, this is to fix it with
rs6000_constraints[RS6000_CONSTRAINT_v] to align with some other
existing register constraints with RS6000_CONSTRAINT_*.

gcc/ChangeLog:

	* config/rs6000/constraints.md (register constraint v): Use
	rs6000_constraints[RS6000_CONSTRAINT_v] instead of ALTIVEC_REGS.
---

diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 7aaffd9f9a8..b361893e289 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -37,7 +37,7 @@
    historically @code{f} was for single-precision and @code{d} was for
    double-precision floating point.")
 
-(define_register_constraint "v" "ALTIVEC_REGS"
+(define_register_constraint "v" "rs6000_constraints[RS6000_CONSTRAINT_v]"
   "An Altivec vector register (VR), @code{v0}@dots{}@code{v31}.")
 
 (define_register_constraint "wa" "rs6000_constraints[RS6000_CONSTRAINT_wa]"