From: Alice Carlotti Date: Tue, 2 Sep 2025 14:49:40 +0000 (+0100) Subject: aarch64: Make spmzr_el0 write-only X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=563f41735224432457a2a977e740560b62d3ec10;p=thirdparty%2Fbinutils-gdb.git aarch64: Make spmzr_el0 write-only Remove all test cases that expect spmzr_el0 to be readable, and remove some redundant default macro values from armv9_5-a-sysregs.s while we're there. Add a read of spmzr_el0 to sysreg-diagnostics.s. This turns out to be the first test for the "reading from a write-only register" note. Also remove the recently added -menable-sysreg-checking option from this test, both to simplify the addition of spmzr_el0 to the test, and to verify that read/write diagnostics don't depend on that option. --- diff --git a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.l b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.l index 58e7f9b9c26..41d89ac281d 100644 --- a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.l +++ b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs-archv9_4-unsupported.l @@ -9,9 +9,7 @@ [^ :]+:[0-9]+: Info: macro invoked from here [^ :]+:[0-9]+: Error: selected processor does not support system register name 'spmzr_el0' [^ :]+:[0-9]+: Info: macro invoked from here -[^ :]+:[0-9]+: Error: selected processor does not support system register name 'spmzr_el0' -[^ :]+:[0-9]+: Info: macro invoked from here [^ :]+:[0-9]+: Error: selected processor does not support system register name 'mdstepop_el1' [^ :]+:[0-9]+: Info: macro invoked from here [^ :]+:[0-9]+: Error: selected processor does not support system register name 'mdstepop_el1' -[^ :]+:[0-9]+: Info: macro invoked from here \ No newline at end of file +[^ :]+:[0-9]+: Info: macro invoked from here diff --git a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d index 55a534eaa4c..8c9f4980024 100644 --- a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d +++ b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.d @@ -12,6 +12,5 @@ Disassembly of section \.text: .*: d51e5260 msr vsesr_el3, x0 .*: d53e5260 mrs x0, vsesr_el3 .*: d5139c80 msr spmzr_el0, x0 -.*: d5339c80 mrs x0, spmzr_el0 .*: d5100540 msr mdstepop_el1, x0 .*: d5300540 mrs x0, mdstepop_el1 diff --git a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.s b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.s index e3ba989c88e..96e4fde6ce0 100644 --- a/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.s +++ b/gas/testsuite/gas/aarch64/sysreg/armv9_5-a-sysregs.s @@ -3,11 +3,11 @@ .text /* Delegated SError exceptions for EL3. */ -rw_sys_reg sys_reg=vdisr_el3 xreg=x0 r=1 w=1 -rw_sys_reg sys_reg=vsesr_el3 xreg=x0 r=1 w=1 +rw_sys_reg vdisr_el3 +rw_sys_reg vsesr_el3 /* System Performance Monitors Extension version 2. */ -rw_sys_reg sys_reg=spmzr_el0 xreg=x0 r=1 w=1 +rw_sys_reg spmzr_el0 r=0 /* Enhanced Software Step Extension. */ -rw_sys_reg sys_reg=mdstepop_el1 xreg=x0 r=1 w=1 +rw_sys_reg mdstepop_el1 diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-diagnostic.d b/gas/testsuite/gas/aarch64/sysreg/sysreg-diagnostic.d index 35267f578aa..e88d74ee215 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-diagnostic.d +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-diagnostic.d @@ -1,5 +1,5 @@ #objdump: -dr -M notes -#as: -menable-sysreg-checking -march=armv8-a +#as: -march=armv8-a #warning_output: sysreg-diagnostic.l .*: file format .* @@ -14,3 +14,4 @@ Disassembly of section \.text: .*: d5180003 msr midr_el1, x3 // note: writing to a read-only register .*: d5180640 msr id_aa64isar2_el1, x0 // note: writing to a read-only register .*: d5180660 msr id_aa64isar3_el1, x0 // note: writing to a read-only register +.*: d5339c80 mrs x0, spmzr_el0 // note: reading from a write-only register diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-diagnostic.l b/gas/testsuite/gas/aarch64/sysreg/sysreg-diagnostic.l index df3d3e572a9..384f0730d15 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-diagnostic.l +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-diagnostic.l @@ -4,3 +4,4 @@ .*:6: Warning: specified register cannot be written to at operand 1 -- `msr midr_el1,x3' .*:7: Warning: specified register cannot be written to at operand 1 -- `msr id_aa64isar2_el1,x0' .*:8: Warning: specified register cannot be written to at operand 1 -- `msr id_aa64isar3_el1,x0' +.*: Warning: specified register cannot be read from at operand 2 -- `mrs x0,spmzr_el0' diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-diagnostic.s b/gas/testsuite/gas/aarch64/sysreg/sysreg-diagnostic.s index d8e48c682a5..607309576fe 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysreg-diagnostic.s +++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-diagnostic.s @@ -6,3 +6,4 @@ msr midr_el1, x3 msr id_aa64isar2_el1, x0 msr id_aa64isar3_el1, x0 + mrs x0, spmzr_el0 diff --git a/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions-bad.l b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions-bad.l index f70dba97e0d..415c8a86d12 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions-bad.l +++ b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions-bad.l @@ -107,8 +107,6 @@ .*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'spmzr_el0' .*: Info: macro invoked from here -.*: Error: selected processor does not support system register name 'spmzr_el0' -.*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'mdstepop_el1' .*: Info: macro invoked from here .*: Error: selected processor does not support system register name 'mdstepop_el1' diff --git a/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions.d b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions.d index f311c23cdae..ac5d1721338 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions.d +++ b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions.d @@ -59,7 +59,6 @@ .*: d51ec120 msr vdisr_el3, x0 .*: d53ec120 mrs x0, vdisr_el3 .*: d5139c80 msr spmzr_el0, x0 -.*: d5339c80 mrs x0, spmzr_el0 .*: d5100540 msr mdstepop_el1, x0 .*: d5300540 mrs x0, mdstepop_el1 .*: d51e21a0 msr gpcbw_el3, x0 diff --git a/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions.s b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions.s index f5c1138ada1..89e7388c1dc 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions.s +++ b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions.s @@ -30,7 +30,7 @@ rw_sys_reg pmccntsvr_el1 w=0 // PMUv3_SS rw_sys_reg vdisr_el3 // E3DES - rw_sys_reg spmzr_el0 // SPMU2 + rw_sys_reg spmzr_el0 r=0 // SPMU2 rw_sys_reg mdstepop_el1 // STEP2 rw_sys_reg gpcbw_el3 // V9_5A diff --git a/gas/testsuite/gas/aarch64/sysreg/sysregs_with_restrictions.d b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_restrictions.d index bca119d76f3..38cc6ddc82f 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysregs_with_restrictions.d +++ b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_restrictions.d @@ -59,7 +59,6 @@ .*: d51ec120 msr vdisr_el3, x0 .*: d53ec120 mrs x0, vdisr_el3 .*: d5139c80 msr spmzr_el0, x0 -.*: d5339c80 mrs x0, spmzr_el0 .*: d5100540 msr mdstepop_el1, x0 .*: d5300540 mrs x0, mdstepop_el1 .*: d51e21a0 msr gpcbw_el3, x0 diff --git a/gas/testsuite/gas/aarch64/sysreg/sysregs_with_restrictions.s b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_restrictions.s index 0cdb822fdf4..7f95777144b 100644 --- a/gas/testsuite/gas/aarch64/sysreg/sysregs_with_restrictions.s +++ b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_restrictions.s @@ -49,7 +49,7 @@ .arch armv9.5-a rw_sys_reg vdisr_el3 // E3DES - rw_sys_reg spmzr_el0 // SPMU2 + rw_sys_reg spmzr_el0 r=0 // SPMU2 rw_sys_reg mdstepop_el1 // STEP2 rw_sys_reg gpcbw_el3 // V9_5A diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def index 31ae528a742..4577b96819c 100644 --- a/opcodes/aarch64-sys-regs.def +++ b/opcodes/aarch64-sys-regs.def @@ -971,7 +971,7 @@ SYSREG ("spmrootcr_el3", CPENC (2,6,9,14,7), 0, AARCH64_FEATURE (SPMU)) SYSREG ("spmscr_el1", CPENC (2,7,9,14,7), 0, AARCH64_FEATURE (SPMU)) SYSREG ("spmselr_el0", CPENC (2,3,9,12,5), 0, AARCH64_FEATURE (SPMU)) - SYSREG ("spmzr_el0", CPENC (2,3,9,12,4), 0, AARCH64_FEATURE (SPMU2)) + SYSREG ("spmzr_el0", CPENC (2,3,9,12,4), F_REG_WRITE, AARCH64_FEATURE (SPMU2)) SYSREG ("spsel", CPENC (3,0,4,2,0), 0, AARCH64_NO_FEATURES) SYSREG ("spsr_abt", CPENC (3,4,4,3,1), 0, AARCH64_NO_FEATURES) SYSREG ("spsr_el1", CPENC (3,0,4,0,0), 0, AARCH64_NO_FEATURES)