From: Kito Cheng <kito.cheng@sifive.com>
Date: Fri, 19 Jan 2024 02:30:16 +0000 (+0800)
Subject: RISC-V: Tweak the wording for the sorry message
X-Git-Tag: basepoints/gcc-15~1874
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=565935f93a7da629da89b05812a3e8c43287598f;p=thirdparty%2Fgcc.git

RISC-V: Tweak the wording for the sorry message

Use "does not" rather than "cannot", because it's implementation issue.

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_override_options_internal): Tweak
	sorry message.
---

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index f1d5129397fb..dd6e68a08c22 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -8798,13 +8798,13 @@ riscv_override_options_internal (struct gcc_options *opts)
 
      We can only allow TARGET_MIN_VLEN * 8 (LMUL) < 65535.  */
   if (TARGET_MIN_VLEN_OPTS (opts) > 4096)
-    sorry ("Current RISC-V GCC cannot support VLEN greater than 4096bit for "
+    sorry ("Current RISC-V GCC does not support VLEN greater than 4096bit for "
 	   "'V' Extension");
 
   /* FIXME: We don't support RVV in big-endian for now, we may enable RVV with
      big-endian after finishing full coverage testing.  */
   if (TARGET_VECTOR && TARGET_BIG_ENDIAN)
-    sorry ("Current RISC-V GCC cannot support RVV in big-endian mode");
+    sorry ("Current RISC-V GCC does not support RVV in big-endian mode");
 
   /* Convert -march to a chunks count.  */
   riscv_vector_chunks = riscv_convert_vector_bits (opts);