From: Greg Kroah-Hartman Date: Mon, 6 Oct 2025 10:08:43 +0000 (+0200) Subject: 6.16-stable patches X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=5668eca41bd5a3c0c03917b92d31b9c8cad0f4c0;p=thirdparty%2Fkernel%2Fstable-queue.git 6.16-stable patches added patches: alsa-hda-tas2781-fix-the-order-of-tas2781-calibrated-data.patch drm-amdgpu-enable-mes-lr_compute_wa-by-default.patch series --- diff --git a/queue-6.16/alsa-hda-tas2781-fix-the-order-of-tas2781-calibrated-data.patch b/queue-6.16/alsa-hda-tas2781-fix-the-order-of-tas2781-calibrated-data.patch new file mode 100644 index 0000000000..e1fe43b96a --- /dev/null +++ b/queue-6.16/alsa-hda-tas2781-fix-the-order-of-tas2781-calibrated-data.patch @@ -0,0 +1,71 @@ +From 71d2893a235bf3b95baccead27b3d47f2f2cdc4c Mon Sep 17 00:00:00 2001 +From: Shenghao Ding +Date: Mon, 8 Sep 2025 06:27:27 +0800 +Subject: ALSA: hda/tas2781: Fix the order of TAS2781 calibrated-data + +From: Shenghao Ding + +commit 71d2893a235bf3b95baccead27b3d47f2f2cdc4c upstream. + +A bug reported by one of my customers that the order of TAS2781 +calibrated-data is incorrect, the correct way is to move R0_Low +and insert it between R0 and InvR0. + +Fixes: 4fe238513407 ("ALSA: hda/tas2781: Move and unified the calibrated-data getting function for SPI and I2C into the tas2781_hda lib") +Signed-off-by: Shenghao Ding +Link: https://patch.msgid.link/20250907222728.988-1-shenghao-ding@ti.com +Signed-off-by: Takashi Iwai +Cc: Gergo Koteles +Signed-off-by: Greg Kroah-Hartman +--- + sound/pci/hda/tas2781_hda.c | 25 ++++++++++++++++++++----- + 1 file changed, 20 insertions(+), 5 deletions(-) + +--- a/sound/pci/hda/tas2781_hda.c ++++ b/sound/pci/hda/tas2781_hda.c +@@ -31,6 +31,23 @@ const efi_guid_t tasdev_fct_efi_guid[] = + }; + EXPORT_SYMBOL_NS_GPL(tasdev_fct_efi_guid, "SND_HDA_SCODEC_TAS2781"); + ++/* ++ * The order of calibrated-data writing function is a bit different from the ++ * order in UEFI. Here is the conversion to match the order of calibrated-data ++ * writing function. ++ */ ++static void cali_cnv(unsigned char *data, unsigned int base, int offset) ++{ ++ struct cali_reg reg_data; ++ ++ memcpy(®_data, &data[base], sizeof(reg_data)); ++ /* the data order has to be swapped between r0_low_reg and inv0_reg */ ++ swap(reg_data.r0_low_reg, reg_data.invr0_reg); ++ ++ cpu_to_be32_array((__force __be32 *)(data + offset + 1), ++ (u32 *)®_data, TASDEV_CALIB_N); ++} ++ + static void tas2781_apply_calib(struct tasdevice_priv *p) + { + struct calidata *cali_data = &p->cali_data; +@@ -101,8 +118,7 @@ static void tas2781_apply_calib(struct t + + data[l] = k; + oft++; +- for (i = 0; i < TASDEV_CALIB_N * 4; i++) +- data[l + i + 1] = data[4 * oft + i]; ++ cali_cnv(data, 4 * oft, l); + k++; + } + } +@@ -128,9 +144,8 @@ static void tas2781_apply_calib(struct t + + for (j = p->ndev - 1; j >= 0; j--) { + l = j * (cali_data->cali_dat_sz_per_dev + 1); +- for (i = TASDEV_CALIB_N * 4; i > 0 ; i--) +- data[l + i] = data[p->index * 5 + i]; +- data[l+i] = j; ++ cali_cnv(data, cali_data->cali_dat_sz_per_dev * j, l); ++ data[l] = j; + } + } + diff --git a/queue-6.16/drm-amdgpu-enable-mes-lr_compute_wa-by-default.patch b/queue-6.16/drm-amdgpu-enable-mes-lr_compute_wa-by-default.patch new file mode 100644 index 0000000000..6a71558f58 --- /dev/null +++ b/queue-6.16/drm-amdgpu-enable-mes-lr_compute_wa-by-default.patch @@ -0,0 +1,80 @@ +From 1fb710793ce2619223adffaf981b1ff13cd48f17 Mon Sep 17 00:00:00 2001 +From: Mario Limonciello +Date: Thu, 18 Sep 2025 19:48:00 -0500 +Subject: drm/amdgpu: Enable MES lr_compute_wa by default + +From: Mario Limonciello + +commit 1fb710793ce2619223adffaf981b1ff13cd48f17 upstream. + +The MES set resources packet has an optional bit 'lr_compute_wa' +which can be used for preventing MES hangs on long compute jobs. + +Set this bit by default. + +Co-developed-by: Yifan Zhang +Signed-off-by: Yifan Zhang +Acked-by: Alex Deucher +Signed-off-by: Mario Limonciello +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 6 ++++++ + drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 5 +++++ + drivers/gpu/drm/amd/include/mes_v11_api_def.h | 3 ++- + drivers/gpu/drm/amd/include/mes_v12_api_def.h | 3 ++- + 4 files changed, 15 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +@@ -711,6 +711,12 @@ static int mes_v11_0_set_hw_resources(st + mes_set_hw_res_pkt.enable_reg_active_poll = 1; + mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; + mes_set_hw_res_pkt.oversubscription_timer = 50; ++ if ((mes->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x7f) ++ mes_set_hw_res_pkt.enable_lr_compute_wa = 1; ++ else ++ dev_info_once(mes->adev->dev, ++ "MES FW version must be >= 0x7f to enable LR compute workaround.\n"); ++ + if (amdgpu_mes_log_enable) { + mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; + mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = +--- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +@@ -738,6 +738,11 @@ static int mes_v12_0_set_hw_resources(st + mes_set_hw_res_pkt.use_different_vmid_compute = 1; + mes_set_hw_res_pkt.enable_reg_active_poll = 1; + mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; ++ if ((mes->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x82) ++ mes_set_hw_res_pkt.enable_lr_compute_wa = 1; ++ else ++ dev_info_once(adev->dev, ++ "MES FW version must be >= 0x82 to enable LR compute workaround.\n"); + + /* + * Keep oversubscribe timer for sdma . When we have unmapped doorbell +--- a/drivers/gpu/drm/amd/include/mes_v11_api_def.h ++++ b/drivers/gpu/drm/amd/include/mes_v11_api_def.h +@@ -238,7 +238,8 @@ union MESAPI_SET_HW_RESOURCES { + uint32_t enable_mes_sch_stb_log : 1; + uint32_t limit_single_process : 1; + uint32_t is_strix_tmz_wa_enabled :1; +- uint32_t reserved : 13; ++ uint32_t enable_lr_compute_wa : 1; ++ uint32_t reserved : 12; + }; + uint32_t uint32_t_all; + }; +--- a/drivers/gpu/drm/amd/include/mes_v12_api_def.h ++++ b/drivers/gpu/drm/amd/include/mes_v12_api_def.h +@@ -286,7 +286,8 @@ union MESAPI_SET_HW_RESOURCES { + uint32_t limit_single_process : 1; + uint32_t unmapped_doorbell_handling: 2; + uint32_t enable_mes_fence_int: 1; +- uint32_t reserved : 10; ++ uint32_t enable_lr_compute_wa : 1; ++ uint32_t reserved : 9; + }; + uint32_t uint32_all; + }; diff --git a/queue-6.16/series b/queue-6.16/series new file mode 100644 index 0000000000..7e7bd8e961 --- /dev/null +++ b/queue-6.16/series @@ -0,0 +1,2 @@ +alsa-hda-tas2781-fix-the-order-of-tas2781-calibrated-data.patch +drm-amdgpu-enable-mes-lr_compute_wa-by-default.patch