From: Greg Kroah-Hartman Date: Tue, 11 Apr 2023 11:05:36 +0000 (+0200) Subject: 5.15-stable patches X-Git-Tag: v5.15.107~36 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=5709ac0627f1dd0d8619c2669acdf8dbf8a822fb;p=thirdparty%2Fkernel%2Fstable-queue.git 5.15-stable patches added patches: coresight-etm4-fix-for-loop-drvdata-nr_addr_cmp-range-bug.patch coresight-etm4x-do-not-access-trcidr1-for-identification.patch --- diff --git a/queue-5.15/coresight-etm4-fix-for-loop-drvdata-nr_addr_cmp-range-bug.patch b/queue-5.15/coresight-etm4-fix-for-loop-drvdata-nr_addr_cmp-range-bug.patch new file mode 100644 index 00000000000..cc180e4ffa4 --- /dev/null +++ b/queue-5.15/coresight-etm4-fix-for-loop-drvdata-nr_addr_cmp-range-bug.patch @@ -0,0 +1,33 @@ +From bf84937e882009075f57fd213836256fc65d96bc Mon Sep 17 00:00:00 2001 +From: Steve Clevenger +Date: Mon, 27 Feb 2023 16:54:32 -0700 +Subject: coresight-etm4: Fix for() loop drvdata->nr_addr_cmp range bug + +From: Steve Clevenger + +commit bf84937e882009075f57fd213836256fc65d96bc upstream. + +In etm4_enable_hw, fix for() loop range to represent address comparator pairs. + +Fixes: 2e1cdfe184b5 ("coresight-etm4x: Adding CoreSight ETM4x driver") +Cc: stable@vger.kernel.org +Signed-off-by: Steve Clevenger +Reviewed-by: James Clark +Signed-off-by: Suzuki K Poulose +Link: https://lore.kernel.org/r/4a4ee61ce8ef402615a4528b21a051de3444fb7b.1677540079.git.scclevenger@os.amperecomputing.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/hwtracing/coresight/coresight-etm4x-core.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c ++++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c +@@ -411,7 +411,7 @@ static int etm4_enable_hw(struct etmv4_d + if (etm4x_sspcicrn_present(drvdata, i)) + etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i)); + } +- for (i = 0; i < drvdata->nr_addr_cmp; i++) { ++ for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) { + etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i)); + etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i)); + } diff --git a/queue-5.15/coresight-etm4x-do-not-access-trcidr1-for-identification.patch b/queue-5.15/coresight-etm4x-do-not-access-trcidr1-for-identification.patch new file mode 100644 index 00000000000..6168e0d13cd --- /dev/null +++ b/queue-5.15/coresight-etm4x-do-not-access-trcidr1-for-identification.patch @@ -0,0 +1,113 @@ +From 735e7b30a53a1679c050cddb73f5e5316105d2e3 Mon Sep 17 00:00:00 2001 +From: Suzuki K Poulose +Date: Tue, 21 Mar 2023 10:45:30 +0000 +Subject: coresight: etm4x: Do not access TRCIDR1 for identification + +From: Suzuki K Poulose + +commit 735e7b30a53a1679c050cddb73f5e5316105d2e3 upstream. + +CoreSight ETM4x architecture clearly provides ways to identify a device +via registers in the "Management" class, TRCDEVARCH and TRCDEVTYPE. These +registers can be accessed without the Trace domain being powered on. +We additionally added TRCIDR1 as fallback in order to cover for any +ETMs that may not have implemented TRCDEVARCH. So far, nobody has +reported hitting a WARNING we placed to catch such systems. + +Also, more importantly it is problematic to access TRCIDR1, which is a +"Trace" register via MMIO access, without clearing the OSLK. But we cannot +mess with the OSLK until we know for sure that this is an ETMv4 device. +Thus, this kind of creates a chicken and egg problem unnecessarily for +systems "which are compliant" to the ETMv4 architecture. + +Let us remove the TRCIDR1 fall back check and rely only on TRCDEVARCH. + +Fixes: 8b94db1edaee ("coresight: etm4x: Use TRCDEVARCH for component discovery") +Cc: stable@vger.kernel.org +Reported-by: Steve Clevenger +Link: https://lore.kernel.org/all/143540e5623d4c7393d24833f2b80600d8d745d2.1677881753.git.scclevenger@os.amperecomputing.com/ +Cc: Mike Leach +Cc: James Clark +Reviewed-by: Mike Leach +Reviewed-by: Anshuman Khandual +Signed-off-by: Suzuki K Poulose +Link: https://lore.kernel.org/r/20230321104530.1547136-1-suzuki.poulose@arm.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/hwtracing/coresight/coresight-etm4x-core.c | 22 ++++++++------------- + drivers/hwtracing/coresight/coresight-etm4x.h | 20 +++++-------------- + 2 files changed, 15 insertions(+), 27 deletions(-) + +--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c ++++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c +@@ -951,25 +951,21 @@ static bool etm4_init_iomem_access(struc + struct csdev_access *csa) + { + u32 devarch = readl_relaxed(drvdata->base + TRCDEVARCH); +- u32 idr1 = readl_relaxed(drvdata->base + TRCIDR1); + + /* + * All ETMs must implement TRCDEVARCH to indicate that +- * the component is an ETMv4. To support any broken +- * implementations we fall back to TRCIDR1 check, which +- * is not really reliable. ++ * the component is an ETMv4. Even though TRCIDR1 also ++ * contains the information, it is part of the "Trace" ++ * register and must be accessed with the OSLK cleared, ++ * with MMIO. But we cannot touch the OSLK until we are ++ * sure this is an ETM. So rely only on the TRCDEVARCH. + */ +- if ((devarch & ETM_DEVARCH_ID_MASK) == ETM_DEVARCH_ETMv4x_ARCH) { +- drvdata->arch = etm_devarch_to_arch(devarch); +- } else { +- pr_warn("CPU%d: ETM4x incompatible TRCDEVARCH: %x, falling back to TRCIDR1\n", +- smp_processor_id(), devarch); +- +- if (ETM_TRCIDR1_ARCH_MAJOR(idr1) != ETM_TRCIDR1_ARCH_ETMv4) +- return false; +- drvdata->arch = etm_trcidr_to_arch(idr1); ++ if ((devarch & ETM_DEVARCH_ID_MASK) != ETM_DEVARCH_ETMv4x_ARCH) { ++ pr_warn_once("TRCDEVARCH doesn't match ETMv4 architecture\n"); ++ return false; + } + ++ drvdata->arch = etm_devarch_to_arch(devarch); + *csa = CSDEV_ACCESS_IOMEM(drvdata->base); + return true; + } +--- a/drivers/hwtracing/coresight/coresight-etm4x.h ++++ b/drivers/hwtracing/coresight/coresight-etm4x.h +@@ -669,14 +669,12 @@ + * TRCDEVARCH - CoreSight architected register + * - Bits[15:12] - Major version + * - Bits[19:16] - Minor version +- * TRCIDR1 - ETM architected register +- * - Bits[11:8] - Major version +- * - Bits[7:4] - Minor version +- * We must rely on TRCDEVARCH for the version information, +- * however we don't want to break the support for potential +- * old implementations which might not implement it. Thus +- * we fall back to TRCIDR1 if TRCDEVARCH is not implemented +- * for memory mapped components. ++ * ++ * We must rely only on TRCDEVARCH for the version information. Even though, ++ * TRCIDR1 also provides the architecture version, it is a "Trace" register ++ * and as such must be accessed only with Trace power domain ON. This may ++ * not be available at probe time. ++ * + * Now to make certain decisions easier based on the version + * we use an internal representation of the version in the + * driver, as follows : +@@ -702,12 +700,6 @@ static inline u8 etm_devarch_to_arch(u32 + ETM_DEVARCH_REVISION(devarch)); + } + +-static inline u8 etm_trcidr_to_arch(u32 trcidr1) +-{ +- return ETM_ARCH_VERSION(ETM_TRCIDR1_ARCH_MAJOR(trcidr1), +- ETM_TRCIDR1_ARCH_MINOR(trcidr1)); +-} +- + enum etm_impdef_type { + ETM4_IMPDEF_HISI_CORE_COMMIT, + ETM4_IMPDEF_FEATURE_MAX, diff --git a/queue-5.15/series b/queue-5.15/series index 0c190b11ff4..58cee1903cd 100644 --- a/queue-5.15/series +++ b/queue-5.15/series @@ -69,6 +69,8 @@ nilfs2-fix-sysfs-interface-lifetime.patch dt-bindings-serial-renesas-scif-fix-4th-irq-for-4-irq-scifs.patch ksmbd-do-not-call-kvmalloc-with-__gfp_noretry-__gfp_no_warn.patch alsa-hda-realtek-add-quirk-for-clevo-x370snw.patch +coresight-etm4x-do-not-access-trcidr1-for-identification.patch +coresight-etm4-fix-for-loop-drvdata-nr_addr_cmp-range-bug.patch iio-adc-ad7791-fix-irq-flags.patch scsi-qla2xxx-fix-memory-leak-in-qla2x00_probe_one.patch scsi-iscsi_tcp-check-that-sock-is-valid-before-iscsi.patch