From: belagod <belagod@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Fri, 22 Nov 2013 15:27:23 +0000 (+0000)
Subject: 2013-11-22  Tejas Belagod  <tejas.belagod@arm.com>
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=571ec0acd37b50a5c6f2508c55912a2eb45f5f35;p=thirdparty%2Fgcc.git

2013-11-22  Tejas Belagod  <tejas.belagod@arm.com>

gcc/
	* config/aarch64/aarch64-simd.md (*aarch64_simd_mov<mode>): Fix loads
	and stores to be ABI compliant.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@205266 138bc75d-0d04-0410-961f-82ee72b054a4
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 15459d3e3072..835030e4cb5f 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2013-11-22  Tejas Belagod  <tejas.belagod@arm.com>
+
+	* config/aarch64/aarch64-simd.md (*aarch64_simd_mov<mode>): Fix loads
+	and stores to be ABI compliant.
+
 2013-11-22  David Malcolm  <dmalcolm@redhat.com>
 
 	* input.h (input_line): Remove.
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index b9ebdf54431f..19ef2030bb01 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -85,17 +85,17 @@
 
 (define_insn "*aarch64_simd_mov<mode>"
   [(set (match_operand:VD 0 "aarch64_simd_nonimmediate_operand"
-		"=w, Utv,  w, ?r, ?w, ?r, w")
+		"=w, m,  w, ?r, ?w, ?r, w")
 	(match_operand:VD 1 "aarch64_simd_general_operand"
-		"Utv,  w,  w,  w,  r,  r, Dn"))]
+		"m,  w,  w,  w,  r,  r, Dn"))]
   "TARGET_SIMD
    && (register_operand (operands[0], <MODE>mode)
        || register_operand (operands[1], <MODE>mode))"
 {
    switch (which_alternative)
      {
-     case 0: return "ld1\t{%0.<Vtype>}, %1";
-     case 1: return "st1\t{%1.<Vtype>}, %0";
+     case 0: return "ldr\\t%d0, %1";
+     case 1: return "str\\t%d1, %0";
      case 2: return "orr\t%0.<Vbtype>, %1.<Vbtype>, %1.<Vbtype>";
      case 3: return "umov\t%0, %1.d[0]";
      case 4: return "ins\t%0.d[0], %1";
@@ -113,9 +113,9 @@
 
 (define_insn "*aarch64_simd_mov<mode>"
   [(set (match_operand:VQ 0 "aarch64_simd_nonimmediate_operand"
-		"=w, Utv,  w, ?r, ?w, ?r, w")
+		"=w, m,  w, ?r, ?w, ?r, w")
 	(match_operand:VQ 1 "aarch64_simd_general_operand"
-		"Utv,  w,  w,  w,  r,  r, Dn"))]
+		"m,  w,  w,  w,  r,  r, Dn"))]
   "TARGET_SIMD
    && (register_operand (operands[0], <MODE>mode)
        || register_operand (operands[1], <MODE>mode))"
@@ -123,9 +123,9 @@
   switch (which_alternative)
     {
     case 0:
-	return "ld1\t{%0.<Vtype>}, %1";
+	return "ldr\\t%q0, %1";
     case 1:
-	return "st1\t{%1.<Vtype>}, %0";
+	return "str\\t%q1, %0";
     case 2:
 	return "orr\t%0.<Vbtype>, %1.<Vbtype>, %1.<Vbtype>";
     case 3: