From: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Date: Tue, 23 Nov 2021 19:05:06 +0000 (+0000)
Subject: arm64: zynqmp: In sck-kr DTS use slg device for GEM phy reset
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=5768e97baf155547660c5082f348309732cf40dd;p=thirdparty%2Fu-boot.git

arm64: zynqmp: In sck-kr DTS use slg device for GEM phy reset

For GEM node switch to phy specific reset-gpios.

Include ethernet-phy-id compatible string in each phy node so that so
that phylib knows the contents of the ID registers.
Some background: In DP83867 external strap configuration is used for PHY
address and strap pin configuration is done by sw stack at a later stage.
The PHY address on power on is configured based on sampled values at
strap pins which is not PHY address mentioned in DT. It could be any PHY
address depending on strap pins default input. For PHY detect to happen
at proper PHY Address we have call PHY reset (RESET_B) after strap pins
are configured otherwise probe (of_mdiobus_phy_device_register) fails
and we see below error:
mdio_bus ff0c0000.ethernet-ffffffff: MDIO device at address 8 is missing.

Apart from reset, it also set proper phy delays.
The TI DP83867 PHY datasheet says:
T1: Post RESET stabilization time == 195us
T3: Hardware configuration pins transition to output drivers == 64us
T4: RESET pulse width == 1us
So with a little overhead set 'reset-assert-us' to 100us (T4) and
'reset-deassert-us' to 280us (T1+T3).

NOTE: The tuning of TI DP83867 phy reset delay is derived from linux
upstream commit: 5dbadc848259(arm64: dts: fsl: add support for Kontron
pitx-imx8m board).

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
---

diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
index 15b01359f28..7fcc288c4d2 100644
--- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
@@ -193,29 +193,32 @@
 	phy-handle = <&phy1>;
 	phy-mode = "rgmii-id";
 
-	mdio: mdio { /* FIXME */
+	mdio: mdio {
 		#address-cells = <1>;
 		#size-cells = <0>;
-		reset-gpios = <&slg7xl45106 6 GPIO_ACTIVE_LOW>;
-		reset-delay-us = <2>;
-
 		phy0: ethernet-phy@4 { /* u81 */
 			#phy-cells = <1>;
+			compatible = "ethernet-phy-id2000.a231";
 			reg = <4>;
 			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
 			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
 			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 			ti,dp83867-rxctrl-strap-quirk;
-			/* This is not correct but address depends on GTR settings */
-			/* reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>;  */
+			reset-assert-us = <100>;
+			reset-deassert-us = <280>;
+			reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>;
 		};
 		phy1: ethernet-phy@8 { /* u36 */
 			#phy-cells = <1>;
+			compatible = "ethernet-phy-id2000.a231";
 			reg = <8>;
 			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
 			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
 			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 			ti,dp83867-rxctrl-strap-quirk;
+			reset-assert-us = <100>;
+			reset-deassert-us = <280>;
+			reset-gpios = <&slg7xl45106 6 GPIO_ACTIVE_LOW>;
 		};
 	};
 };