From: Jonathan Wright Date: Sun, 16 May 2021 12:01:47 +0000 (+0100) Subject: aarch64: Use an expander for quad-word vec_pack_trunc pattern X-Git-Tag: basepoints/gcc-13~7394 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=577d5819e0cada818aca975752809d55ccecc6e8;p=thirdparty%2Fgcc.git aarch64: Use an expander for quad-word vec_pack_trunc pattern The existing vec_pack_trunc RTL pattern emits an opaque two- instruction assembly code sequence that prevents proper instruction scheduling. This commit changes the pattern to an expander that emits individual xtn and xtn2 instructions. This commit also consolidates the duplicate truncation patterns. gcc/ChangeLog: 2021-05-17 Jonathan Wright * config/aarch64/aarch64-simd.md (aarch64_simd_vec_pack_trunc_): Remove as duplicate of... (aarch64_xtn): This. (aarch64_xtn2_le): Move position in file. (aarch64_xtn2_be): Move position in file. (aarch64_xtn2): Move position in file. (vec_pack_trunc_): Define as an expander. --- diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index c67fa3fb6f0c..447b5575f2f5 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1691,14 +1691,51 @@ ;; Narrowing operations. ;; For doubles. -(define_insn "aarch64_simd_vec_pack_trunc_" - [(set (match_operand: 0 "register_operand" "=w") - (truncate: (match_operand:VQN 1 "register_operand" "w")))] - "TARGET_SIMD" - "xtn\\t%0., %1." + +(define_insn "aarch64_xtn" + [(set (match_operand: 0 "register_operand" "=w") + (truncate: (match_operand:VQN 1 "register_operand" "w")))] + "TARGET_SIMD" + "xtn\\t%0., %1." [(set_attr "type" "neon_shift_imm_narrow_q")] ) +(define_insn "aarch64_xtn2_le" + [(set (match_operand: 0 "register_operand" "=w") + (vec_concat: + (match_operand: 1 "register_operand" "0") + (truncate: (match_operand:VQN 2 "register_operand" "w"))))] + "TARGET_SIMD && !BYTES_BIG_ENDIAN" + "xtn2\t%0., %2." + [(set_attr "type" "neon_shift_imm_narrow_q")] +) + +(define_insn "aarch64_xtn2_be" + [(set (match_operand: 0 "register_operand" "=w") + (vec_concat: + (truncate: (match_operand:VQN 2 "register_operand" "w")) + (match_operand: 1 "register_operand" "0")))] + "TARGET_SIMD && BYTES_BIG_ENDIAN" + "xtn2\t%0., %2." + [(set_attr "type" "neon_shift_imm_narrow_q")] +) + +(define_expand "aarch64_xtn2" + [(match_operand: 0 "register_operand") + (match_operand: 1 "register_operand") + (truncate: (match_operand:VQN 2 "register_operand"))] + "TARGET_SIMD" + { + if (BYTES_BIG_ENDIAN) + emit_insn (gen_aarch64_xtn2_be (operands[0], operands[1], + operands[2])); + else + emit_insn (gen_aarch64_xtn2_le (operands[0], operands[1], + operands[2])); + DONE; + } +) + (define_expand "vec_pack_trunc_" [(match_operand: 0 "register_operand") (match_operand:VDN 1 "register_operand") @@ -1711,7 +1748,7 @@ emit_insn (gen_move_lo_quad_ (tempreg, operands[lo])); emit_insn (gen_move_hi_quad_ (tempreg, operands[hi])); - emit_insn (gen_aarch64_simd_vec_pack_trunc_ (operands[0], tempreg)); + emit_insn (gen_aarch64_xtn (operands[0], tempreg)); DONE; }) @@ -1901,20 +1938,25 @@ ;; For quads. -(define_insn "vec_pack_trunc_" - [(set (match_operand: 0 "register_operand" "=&w") +(define_expand "vec_pack_trunc_" + [(set (match_operand: 0 "register_operand") (vec_concat: - (truncate: (match_operand:VQN 1 "register_operand" "w")) - (truncate: (match_operand:VQN 2 "register_operand" "w"))))] + (truncate: (match_operand:VQN 1 "register_operand")) + (truncate: (match_operand:VQN 2 "register_operand"))))] "TARGET_SIMD" { + rtx tmpreg = gen_reg_rtx (mode); + int lo = BYTES_BIG_ENDIAN ? 2 : 1; + int hi = BYTES_BIG_ENDIAN ? 1 : 2; + + emit_insn (gen_aarch64_xtn (tmpreg, operands[lo])); + if (BYTES_BIG_ENDIAN) - return "xtn\\t%0., %2.\;xtn2\\t%0., %1."; + emit_insn (gen_aarch64_xtn2_be (operands[0], tmpreg, operands[hi])); else - return "xtn\\t%0., %1.\;xtn2\\t%0., %2."; + emit_insn (gen_aarch64_xtn2_le (operands[0], tmpreg, operands[hi])); + DONE; } - [(set_attr "type" "multiple") - (set_attr "length" "8")] ) ;; Widening operations. @@ -8570,13 +8612,6 @@ "" ) -(define_expand "aarch64_xtn" - [(set (match_operand: 0 "register_operand" "=w") - (truncate: (match_operand:VQN 1 "register_operand" "w")))] - "TARGET_SIMD" - "" -) - ;; Truncate a 128-bit integer vector to a 64-bit vector. (define_insn "trunc2" [(set (match_operand: 0 "register_operand" "=w") @@ -8586,42 +8621,6 @@ [(set_attr "type" "neon_shift_imm_narrow_q")] ) -(define_insn "aarch64_xtn2_le" - [(set (match_operand: 0 "register_operand" "=w") - (vec_concat: - (match_operand: 1 "register_operand" "0") - (truncate: (match_operand:VQN 2 "register_operand" "w"))))] - "TARGET_SIMD && !BYTES_BIG_ENDIAN" - "xtn2\t%0., %2." - [(set_attr "type" "neon_shift_imm_narrow_q")] -) - -(define_insn "aarch64_xtn2_be" - [(set (match_operand: 0 "register_operand" "=w") - (vec_concat: - (truncate: (match_operand:VQN 2 "register_operand" "w")) - (match_operand: 1 "register_operand" "0")))] - "TARGET_SIMD && BYTES_BIG_ENDIAN" - "xtn2\t%0., %2." - [(set_attr "type" "neon_shift_imm_narrow_q")] -) - -(define_expand "aarch64_xtn2" - [(match_operand: 0 "register_operand") - (match_operand: 1 "register_operand") - (truncate: (match_operand:VQN 2 "register_operand"))] - "TARGET_SIMD" - { - if (BYTES_BIG_ENDIAN) - emit_insn (gen_aarch64_xtn2_be (operands[0], operands[1], - operands[2])); - else - emit_insn (gen_aarch64_xtn2_le (operands[0], operands[1], - operands[2])); - DONE; - } -) - (define_insn "aarch64_bfdot" [(set (match_operand:VDQSF 0 "register_operand" "=w") (plus:VDQSF