From: Greg Kroah-Hartman Date: Sun, 26 Jul 2015 03:51:55 +0000 (-0700) Subject: 4.1-stable patches X-Git-Tag: v4.1.4~48 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=586b2a755d6df48427fd7ea34300e627f27a0463;p=thirdparty%2Fkernel%2Fstable-queue.git 4.1-stable patches added patches: pinctrl-mvebu-armada-370-fix-spi0-pin-description.patch pinctrl-mvebu-armada-375-remove-incorrect-space-in-pin-description.patch pinctrl-mvebu-armada-375-remove-non-existing-nand-re-we-pins.patch pinctrl-mvebu-armada-38x-fix-incorrect-total-number-of-gpios.patch pinctrl-mvebu-armada-38x-fix-pcie-functions.patch pinctrl-mvebu-armada-39x-fix-incorrect-total-number-of-gpios.patch pinctrl-mvebu-armada-xp-fix-functions-of-mpp48.patch pinctrl-mvebu-armada-xp-remove-non-existing-nand-pins.patch pinctrl-mvebu-armada-xp-remove-non-existing-vdd-cpu_pd-functions.patch pinctrl-zynq-fix-define_zynq_pinmux_function_mux-macro.patch pinctrl-zynq-fix-offset-address-for-sd0-sd1-_wp_cd_sel.patch --- diff --git a/queue-4.1/pinctrl-mvebu-armada-370-fix-spi0-pin-description.patch b/queue-4.1/pinctrl-mvebu-armada-370-fix-spi0-pin-description.patch new file mode 100644 index 00000000000..88c9a32dfcd --- /dev/null +++ b/queue-4.1/pinctrl-mvebu-armada-370-fix-spi0-pin-description.patch @@ -0,0 +1,50 @@ +From 438881dfddb9107ef0eb30b49368e91e092f0b3e Mon Sep 17 00:00:00 2001 +From: Thomas Petazzoni +Date: Tue, 9 Jun 2015 18:46:54 +0200 +Subject: pinctrl: mvebu: armada-370: fix spi0 pin description + +From: Thomas Petazzoni + +commit 438881dfddb9107ef0eb30b49368e91e092f0b3e upstream. + +Due to a mistake, the CS0 and CS1 SPI0 functions were incorrectly +named "spi0-1" instead of just "spi0". This commit fixes that. + +This DT binding change does not affect any of the in-tree users. + +Signed-off-by: Thomas Petazzoni +Fixes: 5f597bb2be57 ("pinctrl: mvebu: add pinctrl driver for Armada 370") +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman + +--- + Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt | 4 ++-- + drivers/pinctrl/mvebu/pinctrl-armada-370.c | 4 ++-- + 2 files changed, 4 insertions(+), 4 deletions(-) + +--- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt ++++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt +@@ -92,5 +92,5 @@ mpp61 61 gpo, dev(wen1), u + mpp62 62 gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0), + audio(mclk), uart0(cts) + mpp63 63 gpo, spi0(sck), tclk +-mpp64 64 gpio, spi0(miso), spi0-1(cs1) +-mpp65 65 gpio, spi0(mosi), spi0-1(cs2) ++mpp64 64 gpio, spi0(miso), spi0(cs1) ++mpp65 65 gpio, spi0(mosi), spi0(cs2) +--- a/drivers/pinctrl/mvebu/pinctrl-armada-370.c ++++ b/drivers/pinctrl/mvebu/pinctrl-armada-370.c +@@ -370,11 +370,11 @@ static struct mvebu_mpp_mode mv88f6710_m + MPP_MODE(64, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "spi0", "miso"), +- MPP_FUNCTION(0x2, "spi0-1", "cs1")), ++ MPP_FUNCTION(0x2, "spi0", "cs1")), + MPP_MODE(65, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "spi0", "mosi"), +- MPP_FUNCTION(0x2, "spi0-1", "cs2")), ++ MPP_FUNCTION(0x2, "spi0", "cs2")), + }; + + static struct mvebu_pinctrl_soc_info armada_370_pinctrl_info; diff --git a/queue-4.1/pinctrl-mvebu-armada-375-remove-incorrect-space-in-pin-description.patch b/queue-4.1/pinctrl-mvebu-armada-375-remove-incorrect-space-in-pin-description.patch new file mode 100644 index 00000000000..a2c76f1f133 --- /dev/null +++ b/queue-4.1/pinctrl-mvebu-armada-375-remove-incorrect-space-in-pin-description.patch @@ -0,0 +1,32 @@ +From d538990ee12b162f7ce6c0fcef3b643800102676 Mon Sep 17 00:00:00 2001 +From: Thomas Petazzoni +Date: Tue, 9 Jun 2015 18:46:59 +0200 +Subject: pinctrl: mvebu: armada-375: remove incorrect space in pin description + +From: Thomas Petazzoni + +commit d538990ee12b162f7ce6c0fcef3b643800102676 upstream. + +There was an incorrect space in the definition of the function of one +pin in the Armada 375 pinctrl driver, which this commit fixes. + +Signed-off-by: Thomas Petazzoni +Fixes: ce3ed59dcddd ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 375") +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/pinctrl/mvebu/pinctrl-armada-375.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/pinctrl/mvebu/pinctrl-armada-375.c ++++ b/drivers/pinctrl/mvebu/pinctrl-armada-375.c +@@ -92,7 +92,7 @@ static struct mvebu_mpp_mode mv88f6720_m + MPP_FUNCTION(0x5, "nand", "io1")), + MPP_MODE(8, + MPP_FUNCTION(0x0, "gpio", NULL), +- MPP_FUNCTION(0x1, "dev ", "bootcs"), ++ MPP_FUNCTION(0x1, "dev", "bootcs"), + MPP_FUNCTION(0x2, "spi0", "cs0"), + MPP_FUNCTION(0x3, "spi1", "cs0"), + MPP_FUNCTION(0x5, "nand", "ce")), diff --git a/queue-4.1/pinctrl-mvebu-armada-375-remove-non-existing-nand-re-we-pins.patch b/queue-4.1/pinctrl-mvebu-armada-375-remove-non-existing-nand-re-we-pins.patch new file mode 100644 index 00000000000..f52ff23321d --- /dev/null +++ b/queue-4.1/pinctrl-mvebu-armada-375-remove-non-existing-nand-re-we-pins.patch @@ -0,0 +1,53 @@ +From e5447d26092c72ef3346615ee558c9112ef8063f Mon Sep 17 00:00:00 2001 +From: Thomas Petazzoni +Date: Tue, 9 Jun 2015 18:46:55 +0200 +Subject: pinctrl: mvebu: armada-375: remove non-existing NAND re/we pins + +From: Thomas Petazzoni + +commit e5447d26092c72ef3346615ee558c9112ef8063f upstream. + +After updating to a more recent version of the Armada 375, we realized +that some of the pins documented as having a NAND-related +functionality in fact did not have such functionality. This commit +updates the pinctrl driver accordingly. + +Signed-off-by: Thomas Petazzoni +Fixes: ce3ed59dcddd ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 375") +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman + +--- + Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt | 4 ++-- + drivers/pinctrl/mvebu/pinctrl-armada-375.c | 2 -- + 2 files changed, 2 insertions(+), 4 deletions(-) + +--- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt ++++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt +@@ -22,8 +22,8 @@ mpp5 5 gpio, dev(ad7), s + mpp6 6 gpio, dev(ad0), led(p1), audio(rclk) + mpp7 7 gpio, dev(ad1), ptp(clk), led(p2), audio(extclk) + mpp8 8 gpio, dev (bootcs), spi0(cs0), spi1(cs0) +-mpp9 9 gpio, nf(wen), spi0(sck), spi1(sck) +-mpp10 10 gpio, nf(ren), dram(vttctrl), led(c1) ++mpp9 9 gpio, spi0(sck), spi1(sck), nand(we) ++mpp10 10 gpio, dram(vttctrl), led(c1), nand(re) + mpp11 11 gpio, dev(a0), led(c2), audio(sdo) + mpp12 12 gpio, dev(a1), audio(bclk) + mpp13 13 gpio, dev(readyn), pcie0(rstoutn), pcie1(rstoutn) +--- a/drivers/pinctrl/mvebu/pinctrl-armada-375.c ++++ b/drivers/pinctrl/mvebu/pinctrl-armada-375.c +@@ -98,13 +98,11 @@ static struct mvebu_mpp_mode mv88f6720_m + MPP_FUNCTION(0x5, "nand", "ce")), + MPP_MODE(9, + MPP_FUNCTION(0x0, "gpio", NULL), +- MPP_FUNCTION(0x1, "nf", "wen"), + MPP_FUNCTION(0x2, "spi0", "sck"), + MPP_FUNCTION(0x3, "spi1", "sck"), + MPP_FUNCTION(0x5, "nand", "we")), + MPP_MODE(10, + MPP_FUNCTION(0x0, "gpio", NULL), +- MPP_FUNCTION(0x1, "nf", "ren"), + MPP_FUNCTION(0x2, "dram", "vttctrl"), + MPP_FUNCTION(0x3, "led", "c1"), + MPP_FUNCTION(0x5, "nand", "re"), diff --git a/queue-4.1/pinctrl-mvebu-armada-38x-fix-incorrect-total-number-of-gpios.patch b/queue-4.1/pinctrl-mvebu-armada-38x-fix-incorrect-total-number-of-gpios.patch new file mode 100644 index 00000000000..215d581dcc3 --- /dev/null +++ b/queue-4.1/pinctrl-mvebu-armada-38x-fix-incorrect-total-number-of-gpios.patch @@ -0,0 +1,33 @@ +From 27e7cd016558bf787b128fd882cdd90409ae4036 Mon Sep 17 00:00:00 2001 +From: Thomas Petazzoni +Date: Tue, 9 Jun 2015 18:47:00 +0200 +Subject: pinctrl: mvebu: armada-38x: fix incorrect total number of GPIOs + +From: Thomas Petazzoni + +commit 27e7cd016558bf787b128fd882cdd90409ae4036 upstream. + +The pinctrl_gpio_range[] array described a first bank of 32 GPIOs and +a second one of 27 GPIOs. However, since there is a total of 60 MPP +pins that can be muxed as GPIOs, the second bank really has 28 GPIOs. + +Signed-off-by: Thomas Petazzoni +Fixes: ca6d9a084b56f ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385") +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/pinctrl/mvebu/pinctrl-armada-38x.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c ++++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c +@@ -402,7 +402,7 @@ static struct mvebu_mpp_ctrl armada_38x_ + + static struct pinctrl_gpio_range armada_38x_mpp_gpio_ranges[] = { + MPP_GPIO_RANGE(0, 0, 0, 32), +- MPP_GPIO_RANGE(1, 32, 32, 27), ++ MPP_GPIO_RANGE(1, 32, 32, 28), + }; + + static int armada_38x_pinctrl_probe(struct platform_device *pdev) diff --git a/queue-4.1/pinctrl-mvebu-armada-38x-fix-pcie-functions.patch b/queue-4.1/pinctrl-mvebu-armada-38x-fix-pcie-functions.patch new file mode 100644 index 00000000000..1b7c913cc36 --- /dev/null +++ b/queue-4.1/pinctrl-mvebu-armada-38x-fix-pcie-functions.patch @@ -0,0 +1,253 @@ +From 331642fbf24a1c16b2669ca0a6479b5fcd6dd5b2 Mon Sep 17 00:00:00 2001 +From: Thomas Petazzoni +Date: Tue, 9 Jun 2015 18:46:53 +0200 +Subject: pinctrl: mvebu: armada-38x: fix PCIe functions + +From: Thomas Petazzoni + +commit 331642fbf24a1c16b2669ca0a6479b5fcd6dd5b2 upstream. + +A new revision of the Marvell Armada 38x hardware datasheet unveiled +that the definition of some of the PCIe functions were not +correct. This commit fixes the pinctrl driver accordingly. + +Some PCIe functions simply do not exist, some of the PCIe functions in +fact were corresponding to other functions, and some PCIe functions +have been added. + +Note: the seemingly unrelated removal of spi(cs2) on MPP47 is related: +this function is in fact implemented on MPP43, instead of a PCIe +function. + +Signed-off-by: Thomas Petazzoni +Fixes: ca6d9a084b56f ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 380/385") +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman + +--- + Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt | 38 +++---- + drivers/pinctrl/mvebu/pinctrl-armada-38x.c | 49 ++++------ + 2 files changed, 39 insertions(+), 48 deletions(-) + +--- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt ++++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt +@@ -27,15 +27,15 @@ mpp8 8 gpio, ge0(txd1), + mpp9 9 gpio, ge0(txd2), dev(ad11) + mpp10 10 gpio, ge0(txd3), dev(ad12) + mpp11 11 gpio, ge0(txctl), dev(ad13) +-mpp12 12 gpio, ge0(rxd0), pcie0(rstout), pcie1(rstout) [1], spi0(cs1), dev(ad14) +-mpp13 13 gpio, ge0(rxd1), pcie0(clkreq), pcie1(clkreq) [1], spi0(cs2), dev(ad15) +-mpp14 14 gpio, ge0(rxd2), ptp(clk), m(vtt_ctrl), spi0(cs3), dev(wen1) +-mpp15 15 gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi), pcie1(rstout) [1] +-mpp16 16 gpio, ge0(rxctl), ge(mdio slave), m(decc_err), spi0(miso), pcie0(clkreq) ++mpp12 12 gpio, ge0(rxd0), pcie0(rstout), spi0(cs1), dev(ad14), pcie3(clkreq) ++mpp13 13 gpio, ge0(rxd1), pcie0(clkreq), pcie1(clkreq) [1], spi0(cs2), dev(ad15), pcie2(clkreq) ++mpp14 14 gpio, ge0(rxd2), ptp(clk), m(vtt_ctrl), spi0(cs3), dev(wen1), pcie3(clkreq) ++mpp15 15 gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi) ++mpp16 16 gpio, ge0(rxctl), ge(mdio slave), m(decc_err), spi0(miso), pcie0(clkreq), pcie1(clkreq) [1] + mpp17 17 gpio, ge0(rxclk), ptp(clk), ua1(rxd), spi0(sck), sata1(prsnt) +-mpp18 18 gpio, ge0(rxerr), ptp(trig_gen), ua1(txd), spi0(cs0), pcie1(rstout) [1] +-mpp19 19 gpio, ge0(col), ptp(event_req), pcie0(clkreq), sata1(prsnt), ua0(cts) +-mpp20 20 gpio, ge0(txclk), ptp(clk), pcie1(rstout) [1], sata0(prsnt), ua0(rts) ++mpp18 18 gpio, ge0(rxerr), ptp(trig_gen), ua1(txd), spi0(cs0) ++mpp19 19 gpio, ge0(col), ptp(event_req), ge0(txerr), sata1(prsnt), ua0(cts) ++mpp20 20 gpio, ge0(txclk), ptp(clk), sata0(prsnt), ua0(rts) + mpp21 21 gpio, spi0(cs1), ge1(rxd0), sata0(prsnt), sd0(cmd), dev(bootcs) + mpp22 22 gpio, spi0(mosi), dev(ad0) + mpp23 23 gpio, spi0(sck), dev(ad2) +@@ -58,23 +58,23 @@ mpp39 39 gpio, i2c1(sck), + mpp40 40 gpio, i2c1(sda), ge1(rxd3), ua0(rts), sd0(d2), dev(ad6) + mpp41 41 gpio, ua1(rxd), ge1(rxctl), ua0(cts), spi1(cs3), dev(burst/last) + mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) +-mpp43 43 gpio, pcie0(clkreq), m(vtt_ctrl), m(decc_err), pcie0(rstout), dev(clkout) +-mpp44 44 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [3], pcie0(rstout) +-mpp45 45 gpio, ref(clk_out0), pcie0(rstout), pcie1(rstout) [1], pcie2(rstout), pcie3(rstout) +-mpp46 46 gpio, ref(clk_out1), pcie0(rstout), pcie1(rstout) [1], pcie2(rstout), pcie3(rstout) +-mpp47 47 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], spi1(cs2), sata3(prsnt) [2] +-mpp48 48 gpio, sata0(prsnt), m(vtt_ctrl), tdm2c(pclk), audio(mclk), sd0(d4) +-mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm2c(fsync), audio(lrclk), sd0(d5) +-mpp50 50 gpio, pcie0(rstout), pcie1(rstout) [1], tdm2c(drx), audio(extclk), sd0(cmd) ++mpp43 43 gpio, pcie0(clkreq), m(vtt_ctrl), m(decc_err), spi1(cs2), dev(clkout) ++mpp44 44 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [3] ++mpp45 45 gpio, ref(clk_out0), pcie0(rstout) ++mpp46 46 gpio, ref(clk_out1), pcie0(rstout) ++mpp47 47 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [2] ++mpp48 48 gpio, sata0(prsnt), m(vtt_ctrl), tdm2c(pclk), audio(mclk), sd0(d4), pcie0(clkreq) ++mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm2c(fsync), audio(lrclk), sd0(d5), pcie1(clkreq) ++mpp50 50 gpio, pcie0(rstout), tdm2c(drx), audio(extclk), sd0(cmd) + mpp51 51 gpio, tdm2c(dtx), audio(sdo), m(decc_err) +-mpp52 52 gpio, pcie0(rstout), pcie1(rstout) [1], tdm2c(intn), audio(sdi), sd0(d6) ++mpp52 52 gpio, pcie0(rstout), tdm2c(intn), audio(sdi), sd0(d6) + mpp53 53 gpio, sata1(prsnt), sata0(prsnt), tdm2c(rstn), audio(bclk), sd0(d7) +-mpp54 54 gpio, sata0(prsnt), sata1(prsnt), pcie0(rstout), pcie1(rstout) [1], sd0(d3) ++mpp54 54 gpio, sata0(prsnt), sata1(prsnt), pcie0(rstout), ge0(txerr), sd0(d3) + mpp55 55 gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0) + mpp56 56 gpio, ua1(rts), ge(mdc), m(decc_err), spi1(mosi) + mpp57 57 gpio, spi1(sck), sd0(clk) + mpp58 58 gpio, pcie1(clkreq) [1], i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1) +-mpp59 59 gpio, pcie0(rstout), i2c1(sda), pcie1(rstout) [1], spi1(cs0), sd0(d2) ++mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd0(d2) + + [1]: only available on 88F6820 and 88F6828 + [2]: only available on 88F6828 +--- a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c ++++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c +@@ -94,37 +94,39 @@ static struct mvebu_mpp_mode armada_38x_ + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ge0", "rxd0", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS), +- MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS), + MPP_VAR_FUNCTION(4, "spi0", "cs1", V_88F6810_PLUS), +- MPP_VAR_FUNCTION(5, "dev", "ad14", V_88F6810_PLUS)), ++ MPP_VAR_FUNCTION(5, "dev", "ad14", V_88F6810_PLUS), ++ MPP_VAR_FUNCTION(6, "pcie3", "clkreq", V_88F6810_PLUS)), + MPP_MODE(13, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ge0", "rxd1", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "pcie0", "clkreq", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "pcie1", "clkreq", V_88F6820_PLUS), + MPP_VAR_FUNCTION(4, "spi0", "cs2", V_88F6810_PLUS), +- MPP_VAR_FUNCTION(5, "dev", "ad15", V_88F6810_PLUS)), ++ MPP_VAR_FUNCTION(5, "dev", "ad15", V_88F6810_PLUS), ++ MPP_VAR_FUNCTION(6, "pcie2", "clkreq", V_88F6810_PLUS)), + MPP_MODE(14, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ge0", "rxd2", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "m", "vtt_ctrl", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "spi0", "cs3", V_88F6810_PLUS), +- MPP_VAR_FUNCTION(5, "dev", "wen1", V_88F6810_PLUS)), ++ MPP_VAR_FUNCTION(5, "dev", "wen1", V_88F6810_PLUS), ++ MPP_VAR_FUNCTION(6, "pcie3", "clkreq", V_88F6810_PLUS)), + MPP_MODE(15, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ge0", "rxd3", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ge", "mdc slave", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "pcie0", "rstout", V_88F6810_PLUS), +- MPP_VAR_FUNCTION(4, "spi0", "mosi", V_88F6810_PLUS), +- MPP_VAR_FUNCTION(5, "pcie1", "rstout", V_88F6820_PLUS)), ++ MPP_VAR_FUNCTION(4, "spi0", "mosi", V_88F6810_PLUS)), + MPP_MODE(16, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ge0", "rxctl", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ge", "mdio slave", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "m", "decc_err", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "spi0", "miso", V_88F6810_PLUS), +- MPP_VAR_FUNCTION(5, "pcie0", "clkreq", V_88F6810_PLUS)), ++ MPP_VAR_FUNCTION(5, "pcie0", "clkreq", V_88F6810_PLUS), ++ MPP_VAR_FUNCTION(6, "pcie1", "clkreq", V_88F6820_PLUS)), + MPP_MODE(17, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ge0", "rxclk", V_88F6810_PLUS), +@@ -137,13 +139,12 @@ static struct mvebu_mpp_mode armada_38x_ + MPP_VAR_FUNCTION(1, "ge0", "rxerr", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ptp", "trig_gen", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "ua1", "txd", V_88F6810_PLUS), +- MPP_VAR_FUNCTION(4, "spi0", "cs0", V_88F6810_PLUS), +- MPP_VAR_FUNCTION(5, "pcie1", "rstout", V_88F6820_PLUS)), ++ MPP_VAR_FUNCTION(4, "spi0", "cs0", V_88F6810_PLUS)), + MPP_MODE(19, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ge0", "col", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ptp", "event_req", V_88F6810_PLUS), +- MPP_VAR_FUNCTION(3, "pcie0", "clkreq", V_88F6810_PLUS), ++ MPP_VAR_FUNCTION(3, "ge0", "txerr", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "sata1", "prsnt", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "ua0", "cts", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6810_PLUS)), +@@ -151,7 +152,6 @@ static struct mvebu_mpp_mode armada_38x_ + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ge0", "txclk", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS), +- MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS), + MPP_VAR_FUNCTION(4, "sata0", "prsnt", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "ua0", "rts", V_88F6810_PLUS), + MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6810_PLUS)), +@@ -277,35 +277,27 @@ static struct mvebu_mpp_mode armada_38x_ + MPP_VAR_FUNCTION(1, "pcie0", "clkreq", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "m", "vtt_ctrl", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "m", "decc_err", V_88F6810_PLUS), +- MPP_VAR_FUNCTION(4, "pcie0", "rstout", V_88F6810_PLUS), ++ MPP_VAR_FUNCTION(4, "spi1", "cs2", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "dev", "clkout", V_88F6810_PLUS)), + MPP_MODE(44, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "sata2", "prsnt", V_88F6828), +- MPP_VAR_FUNCTION(4, "sata3", "prsnt", V_88F6828), +- MPP_VAR_FUNCTION(5, "pcie0", "rstout", V_88F6810_PLUS)), ++ MPP_VAR_FUNCTION(4, "sata3", "prsnt", V_88F6828)), + MPP_MODE(45, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ref", "clk_out0", V_88F6810_PLUS), +- MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS), +- MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS), +- MPP_VAR_FUNCTION(4, "pcie2", "rstout", V_88F6810_PLUS), +- MPP_VAR_FUNCTION(5, "pcie3", "rstout", V_88F6810_PLUS)), ++ MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS)), + MPP_MODE(46, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "ref", "clk_out1", V_88F6810_PLUS), +- MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS), +- MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS), +- MPP_VAR_FUNCTION(4, "pcie2", "rstout", V_88F6810_PLUS), +- MPP_VAR_FUNCTION(5, "pcie3", "rstout", V_88F6810_PLUS)), ++ MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS)), + MPP_MODE(47, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "sata2", "prsnt", V_88F6828), +- MPP_VAR_FUNCTION(4, "spi1", "cs2", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "sata3", "prsnt", V_88F6828)), + MPP_MODE(48, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), +@@ -313,18 +305,19 @@ static struct mvebu_mpp_mode armada_38x_ + MPP_VAR_FUNCTION(2, "m", "vtt_ctrl", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "tdm2c", "pclk", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "audio", "mclk", V_88F6810_PLUS), +- MPP_VAR_FUNCTION(5, "sd0", "d4", V_88F6810_PLUS)), ++ MPP_VAR_FUNCTION(5, "sd0", "d4", V_88F6810_PLUS), ++ MPP_VAR_FUNCTION(6, "pcie0", "clkreq", V_88F6810_PLUS)), + MPP_MODE(49, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "sata2", "prsnt", V_88F6828), + MPP_VAR_FUNCTION(2, "sata3", "prsnt", V_88F6828), + MPP_VAR_FUNCTION(3, "tdm2c", "fsync", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "audio", "lrclk", V_88F6810_PLUS), +- MPP_VAR_FUNCTION(5, "sd0", "d5", V_88F6810_PLUS)), ++ MPP_VAR_FUNCTION(5, "sd0", "d5", V_88F6810_PLUS), ++ MPP_VAR_FUNCTION(6, "pcie1", "clkreq", V_88F6820_PLUS)), + MPP_MODE(50, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS), +- MPP_VAR_FUNCTION(2, "pcie1", "rstout", V_88F6820_PLUS), + MPP_VAR_FUNCTION(3, "tdm2c", "drx", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "audio", "extclk", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "sd0", "cmd", V_88F6810_PLUS)), +@@ -336,7 +329,6 @@ static struct mvebu_mpp_mode armada_38x_ + MPP_MODE(52, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS), +- MPP_VAR_FUNCTION(2, "pcie1", "rstout", V_88F6820_PLUS), + MPP_VAR_FUNCTION(3, "tdm2c", "intn", V_88F6810_PLUS), + MPP_VAR_FUNCTION(4, "audio", "sdi", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "sd0", "d6", V_88F6810_PLUS)), +@@ -352,7 +344,7 @@ static struct mvebu_mpp_mode armada_38x_ + MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6810_PLUS), + MPP_VAR_FUNCTION(3, "pcie0", "rstout", V_88F6810_PLUS), +- MPP_VAR_FUNCTION(4, "pcie1", "rstout", V_88F6820_PLUS), ++ MPP_VAR_FUNCTION(4, "ge0", "txerr", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "sd0", "d3", V_88F6810_PLUS)), + MPP_MODE(55, + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), +@@ -382,7 +374,6 @@ static struct mvebu_mpp_mode armada_38x_ + MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), + MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS), + MPP_VAR_FUNCTION(2, "i2c1", "sda", V_88F6810_PLUS), +- MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS), + MPP_VAR_FUNCTION(4, "spi1", "cs0", V_88F6810_PLUS), + MPP_VAR_FUNCTION(5, "sd0", "d2", V_88F6810_PLUS)), + }; diff --git a/queue-4.1/pinctrl-mvebu-armada-39x-fix-incorrect-total-number-of-gpios.patch b/queue-4.1/pinctrl-mvebu-armada-39x-fix-incorrect-total-number-of-gpios.patch new file mode 100644 index 00000000000..8754f44f342 --- /dev/null +++ b/queue-4.1/pinctrl-mvebu-armada-39x-fix-incorrect-total-number-of-gpios.patch @@ -0,0 +1,33 @@ +From 7c580311a2cb3bb0d0188665c9c69227aed650ea Mon Sep 17 00:00:00 2001 +From: Thomas Petazzoni +Date: Tue, 9 Jun 2015 18:47:01 +0200 +Subject: pinctrl: mvebu: armada-39x: fix incorrect total number of GPIOs + +From: Thomas Petazzoni + +commit 7c580311a2cb3bb0d0188665c9c69227aed650ea upstream. + +The pinctrl_gpio_range[] array described a first bank of 32 GPIOs and +a second one of 27 GPIOs. However, since there is a total of 60 MPP +pins that can be muxed as GPIOs, the second bank really has 28 GPIOs. + +Signed-off-by: Thomas Petazzoni +Fixes: ee086577abe7f ("pinctrl: mvebu: add pinctrl driver for Marvell Armada 39x") +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/pinctrl/mvebu/pinctrl-armada-39x.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c ++++ b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c +@@ -380,7 +380,7 @@ static struct mvebu_mpp_ctrl armada_39x_ + + static struct pinctrl_gpio_range armada_39x_mpp_gpio_ranges[] = { + MPP_GPIO_RANGE(0, 0, 0, 32), +- MPP_GPIO_RANGE(1, 32, 32, 27), ++ MPP_GPIO_RANGE(1, 32, 32, 28), + }; + + static int armada_39x_pinctrl_probe(struct platform_device *pdev) diff --git a/queue-4.1/pinctrl-mvebu-armada-xp-fix-functions-of-mpp48.patch b/queue-4.1/pinctrl-mvebu-armada-xp-fix-functions-of-mpp48.patch new file mode 100644 index 00000000000..7ba9d8498ba --- /dev/null +++ b/queue-4.1/pinctrl-mvebu-armada-xp-fix-functions-of-mpp48.patch @@ -0,0 +1,44 @@ +From ea78b9511a54d0de026e04b5da86b30515072f31 Mon Sep 17 00:00:00 2001 +From: Thomas Petazzoni +Date: Tue, 9 Jun 2015 18:46:58 +0200 +Subject: pinctrl: mvebu: armada-xp: fix functions of MPP48 + +From: Thomas Petazzoni + +commit ea78b9511a54d0de026e04b5da86b30515072f31 upstream. + +There was a mistake in the definition of the functions for MPP48 on +Marvell Armada XP. The second function is dev(clkout), and not tclk. + +Signed-off-by: Thomas Petazzoni +Fixes: 463e270f766a ("pinctrl: mvebu: add pinctrl driver for Armada XP") +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman + +--- + Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt | 2 +- + drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +--- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt ++++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +@@ -69,7 +69,7 @@ mpp45 45 gpio, uart2(rts), + mpp46 46 gpio, uart3(rts), uart1(rts), spi(cs6), sata0(prsnt) + mpp47 47 gpio, uart3(cts), uart1(cts), spi(cs7), pcie(clkreq3), + ref(clkout) +-mpp48 48 gpio, tclk, dev(burst/last) ++mpp48 48 gpio, dev(clkout), dev(burst/last) + + * Marvell Armada XP (mv78260 and mv78460 only) + +--- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c ++++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c +@@ -287,7 +287,7 @@ static struct mvebu_mpp_mode armada_xp_m + MPP_VAR_FUNCTION(0x5, "pcie", "clkreq3", V_MV78230_PLUS)), + MPP_MODE(48, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), +- MPP_VAR_FUNCTION(0x1, "tclk", NULL, V_MV78230_PLUS), ++ MPP_VAR_FUNCTION(0x1, "dev", "clkout", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x2, "dev", "burst/last", V_MV78230_PLUS)), + MPP_MODE(49, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), diff --git a/queue-4.1/pinctrl-mvebu-armada-xp-remove-non-existing-nand-pins.patch b/queue-4.1/pinctrl-mvebu-armada-xp-remove-non-existing-nand-pins.patch new file mode 100644 index 00000000000..c7931cbef54 --- /dev/null +++ b/queue-4.1/pinctrl-mvebu-armada-xp-remove-non-existing-nand-pins.patch @@ -0,0 +1,53 @@ +From bc99357f3690c11817756adfee0ece811a3db2e7 Mon Sep 17 00:00:00 2001 +From: Thomas Petazzoni +Date: Tue, 9 Jun 2015 18:46:56 +0200 +Subject: pinctrl: mvebu: armada-xp: remove non-existing NAND pins + +From: Thomas Petazzoni + +commit bc99357f3690c11817756adfee0ece811a3db2e7 upstream. + +After updating to a more recent version of the Armada XP datasheet, we +realized that some of the pins documented as having a NAND-related +functionality in fact did not have such functionality. This commit +updates the pinctrl driver accordingly. + +Signed-off-by: Thomas Petazzoni +Fixes: 463e270f766a ("pinctrl: mvebu: add pinctrl driver for Armada XP") +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman + +--- + Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt | 4 ++-- + drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 2 -- + 2 files changed, 2 insertions(+), 4 deletions(-) + +--- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt ++++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +@@ -42,8 +42,8 @@ mpp20 20 gpio, ge0(rxd4), + mpp21 21 gpio, ge0(rxd5), ge1(rxd3), lcd(d21), mem(bat) + mpp22 22 gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt) + mpp23 23 gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt) +-mpp24 24 gpio, lcd(hsync), sata1(prsnt), nf(bootcs-re), tdm(rst) +-mpp25 25 gpio, lcd(vsync), sata0(prsnt), nf(bootcs-we), tdm(pclk) ++mpp24 24 gpio, lcd(hsync), sata1(prsnt), tdm(rst) ++mpp25 25 gpio, lcd(vsync), sata0(prsnt), tdm(pclk) + mpp26 26 gpio, lcd(clk), tdm(fsync), vdd(cpu1-pd) + mpp27 27 gpio, lcd(e), tdm(dtx), ptp(trig) + mpp28 28 gpio, lcd(pwm), tdm(drx), ptp(evreq) +--- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c ++++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c +@@ -172,13 +172,11 @@ static struct mvebu_mpp_mode armada_xp_m + MPP_MODE(24, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x1, "sata1", "prsnt", V_MV78230_PLUS), +- MPP_VAR_FUNCTION(0x2, "nf", "bootcs-re", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "tdm", "rst", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x4, "lcd", "hsync", V_MV78230_PLUS)), + MPP_MODE(25, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x1, "sata0", "prsnt", V_MV78230_PLUS), +- MPP_VAR_FUNCTION(0x2, "nf", "bootcs-we", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "tdm", "pclk", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x4, "lcd", "vsync", V_MV78230_PLUS)), + MPP_MODE(26, diff --git a/queue-4.1/pinctrl-mvebu-armada-xp-remove-non-existing-vdd-cpu_pd-functions.patch b/queue-4.1/pinctrl-mvebu-armada-xp-remove-non-existing-vdd-cpu_pd-functions.patch new file mode 100644 index 00000000000..ba5ba5a722b --- /dev/null +++ b/queue-4.1/pinctrl-mvebu-armada-xp-remove-non-existing-vdd-cpu_pd-functions.patch @@ -0,0 +1,178 @@ +From 80b3d04feab5e69d51cb2375eb989a7165e43e3b Mon Sep 17 00:00:00 2001 +From: Thomas Petazzoni +Date: Tue, 9 Jun 2015 18:46:57 +0200 +Subject: pinctrl: mvebu: armada-xp: remove non-existing VDD cpu_pd functions + +From: Thomas Petazzoni + +commit 80b3d04feab5e69d51cb2375eb989a7165e43e3b upstream. + +The latest version of the Armada XP datasheet no longer documents the +VDD cpu_pd functions, which might indicate they are not working and/or +not supported. This commit ensures the pinctrl driver matches the +datasheet. + +Signed-off-by: Thomas Petazzoni +Fixes: 463e270f766a ("pinctrl: mvebu: add pinctrl driver for Armada XP") +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman + +--- + Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt | 26 +++---- + drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 33 +++------- + 2 files changed, 20 insertions(+), 39 deletions(-) + +--- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt ++++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +@@ -44,13 +44,13 @@ mpp22 22 gpio, ge0(rxd6), + mpp23 23 gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt) + mpp24 24 gpio, lcd(hsync), sata1(prsnt), tdm(rst) + mpp25 25 gpio, lcd(vsync), sata0(prsnt), tdm(pclk) +-mpp26 26 gpio, lcd(clk), tdm(fsync), vdd(cpu1-pd) ++mpp26 26 gpio, lcd(clk), tdm(fsync) + mpp27 27 gpio, lcd(e), tdm(dtx), ptp(trig) + mpp28 28 gpio, lcd(pwm), tdm(drx), ptp(evreq) +-mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk), vdd(cpu0-pd) ++mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk) + mpp30 30 gpio, tdm(int1), sd0(clk) +-mpp31 31 gpio, tdm(int2), sd0(cmd), vdd(cpu0-pd) +-mpp32 32 gpio, tdm(int3), sd0(d0), vdd(cpu1-pd) ++mpp31 31 gpio, tdm(int2), sd0(cmd) ++mpp32 32 gpio, tdm(int3), sd0(d0) + mpp33 33 gpio, tdm(int4), sd0(d1), mem(bat) + mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt) + mpp35 35 gpio, tdm(int6), sd0(d3), sata1(prsnt) +@@ -58,14 +58,11 @@ mpp36 36 gpio, spi(mosi) + mpp37 37 gpio, spi(miso) + mpp38 38 gpio, spi(sck) + mpp39 39 gpio, spi(cs0) +-mpp40 40 gpio, spi(cs1), uart2(cts), lcd(vga-hsync), vdd(cpu1-pd), +- pcie(clkreq0) ++mpp40 40 gpio, spi(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0) + mpp41 41 gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt), + pcie(clkreq1) +-mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer), +- vdd(cpu0-pd) +-mpp43 43 gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout), +- vdd(cpu2-3-pd){1} ++mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer) ++mpp43 43 gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout) + mpp44 44 gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2), + mem(bat) + mpp45 45 gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt) +@@ -84,9 +81,9 @@ mpp51 51 gpio, dev(ad16) + mpp52 52 gpio, dev(ad17) + mpp53 53 gpio, dev(ad18) + mpp54 54 gpio, dev(ad19) +-mpp55 55 gpio, dev(ad20), vdd(cpu0-pd) +-mpp56 56 gpio, dev(ad21), vdd(cpu1-pd) +-mpp57 57 gpio, dev(ad22), vdd(cpu2-3-pd){1} ++mpp55 55 gpio, dev(ad20) ++mpp56 56 gpio, dev(ad21) ++mpp57 57 gpio, dev(ad22) + mpp58 58 gpio, dev(ad23) + mpp59 59 gpio, dev(ad24) + mpp60 60 gpio, dev(ad25) +@@ -96,6 +93,3 @@ mpp63 63 gpio, dev(ad28) + mpp64 64 gpio, dev(ad29) + mpp65 65 gpio, dev(ad30) + mpp66 66 gpio, dev(ad31) +- +-Notes: +-* {1} vdd(cpu2-3-pd) only available on mv78460. +--- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c ++++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c +@@ -14,10 +14,7 @@ + * available: mv78230, mv78260 and mv78460. From a pin muxing + * perspective, the mv78230 has 49 MPP pins. The mv78260 and mv78460 + * both have 67 MPP pins (more GPIOs and address lines for the memory +- * bus mainly). The only difference between the mv78260 and the +- * mv78460 in terms of pin muxing is the addition of two functions on +- * pins 43 and 56 to access the VDD of the CPU2 and 3 (mv78260 has two +- * cores, mv78460 has four cores). ++ * bus mainly). + */ + + #include +@@ -182,8 +179,7 @@ static struct mvebu_mpp_mode armada_xp_m + MPP_MODE(26, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "tdm", "fsync", V_MV78230_PLUS), +- MPP_VAR_FUNCTION(0x4, "lcd", "clk", V_MV78230_PLUS), +- MPP_VAR_FUNCTION(0x5, "vdd", "cpu1-pd", V_MV78230_PLUS)), ++ MPP_VAR_FUNCTION(0x4, "lcd", "clk", V_MV78230_PLUS)), + MPP_MODE(27, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x1, "ptp", "trig", V_MV78230_PLUS), +@@ -198,8 +194,7 @@ static struct mvebu_mpp_mode armada_xp_m + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x1, "ptp", "clk", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "tdm", "int0", V_MV78230_PLUS), +- MPP_VAR_FUNCTION(0x4, "lcd", "ref-clk", V_MV78230_PLUS), +- MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd", V_MV78230_PLUS)), ++ MPP_VAR_FUNCTION(0x4, "lcd", "ref-clk", V_MV78230_PLUS)), + MPP_MODE(30, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x1, "sd0", "clk", V_MV78230_PLUS), +@@ -207,13 +202,11 @@ static struct mvebu_mpp_mode armada_xp_m + MPP_MODE(31, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x1, "sd0", "cmd", V_MV78230_PLUS), +- MPP_VAR_FUNCTION(0x3, "tdm", "int2", V_MV78230_PLUS), +- MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd", V_MV78230_PLUS)), ++ MPP_VAR_FUNCTION(0x3, "tdm", "int2", V_MV78230_PLUS)), + MPP_MODE(32, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x1, "sd0", "d0", V_MV78230_PLUS), +- MPP_VAR_FUNCTION(0x3, "tdm", "int3", V_MV78230_PLUS), +- MPP_VAR_FUNCTION(0x5, "vdd", "cpu1-pd", V_MV78230_PLUS)), ++ MPP_VAR_FUNCTION(0x3, "tdm", "int3", V_MV78230_PLUS)), + MPP_MODE(33, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x1, "sd0", "d1", V_MV78230_PLUS), +@@ -245,7 +238,6 @@ static struct mvebu_mpp_mode armada_xp_m + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x1, "spi", "cs1", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x2, "uart2", "cts", V_MV78230_PLUS), +- MPP_VAR_FUNCTION(0x3, "vdd", "cpu1-pd", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x4, "lcd", "vga-hsync", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x5, "pcie", "clkreq0", V_MV78230_PLUS)), + MPP_MODE(41, +@@ -260,15 +252,13 @@ static struct mvebu_mpp_mode armada_xp_m + MPP_VAR_FUNCTION(0x1, "uart2", "rxd", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x2, "uart0", "cts", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "tdm", "int7", V_MV78230_PLUS), +- MPP_VAR_FUNCTION(0x4, "tdm-1", "timer", V_MV78230_PLUS), +- MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd", V_MV78230_PLUS)), ++ MPP_VAR_FUNCTION(0x4, "tdm-1", "timer", V_MV78230_PLUS)), + MPP_MODE(43, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x1, "uart2", "txd", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x2, "uart0", "rts", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "spi", "cs3", V_MV78230_PLUS), +- MPP_VAR_FUNCTION(0x4, "pcie", "rstout", V_MV78230_PLUS), +- MPP_VAR_FUNCTION(0x5, "vdd", "cpu2-3-pd", V_MV78460)), ++ MPP_VAR_FUNCTION(0x4, "pcie", "rstout", V_MV78230_PLUS)), + MPP_MODE(44, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x1, "uart2", "cts", V_MV78230_PLUS), +@@ -319,16 +309,13 @@ static struct mvebu_mpp_mode armada_xp_m + MPP_VAR_FUNCTION(0x1, "dev", "ad19", V_MV78260_PLUS)), + MPP_MODE(55, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), +- MPP_VAR_FUNCTION(0x1, "dev", "ad20", V_MV78260_PLUS), +- MPP_VAR_FUNCTION(0x2, "vdd", "cpu0-pd", V_MV78260_PLUS)), ++ MPP_VAR_FUNCTION(0x1, "dev", "ad20", V_MV78260_PLUS)), + MPP_MODE(56, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), +- MPP_VAR_FUNCTION(0x1, "dev", "ad21", V_MV78260_PLUS), +- MPP_VAR_FUNCTION(0x2, "vdd", "cpu1-pd", V_MV78260_PLUS)), ++ MPP_VAR_FUNCTION(0x1, "dev", "ad21", V_MV78260_PLUS)), + MPP_MODE(57, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), +- MPP_VAR_FUNCTION(0x1, "dev", "ad22", V_MV78260_PLUS), +- MPP_VAR_FUNCTION(0x2, "vdd", "cpu2-3-pd", V_MV78460)), ++ MPP_VAR_FUNCTION(0x1, "dev", "ad22", V_MV78260_PLUS)), + MPP_MODE(58, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "ad23", V_MV78260_PLUS)), diff --git a/queue-4.1/pinctrl-zynq-fix-define_zynq_pinmux_function_mux-macro.patch b/queue-4.1/pinctrl-zynq-fix-define_zynq_pinmux_function_mux-macro.patch new file mode 100644 index 00000000000..83cf14378fc --- /dev/null +++ b/queue-4.1/pinctrl-zynq-fix-define_zynq_pinmux_function_mux-macro.patch @@ -0,0 +1,41 @@ +From 4f652cea020aac42972cb7c9788b470ed45aa228 Mon Sep 17 00:00:00 2001 +From: Masahiro Yamada +Date: Wed, 20 May 2015 17:42:30 +0900 +Subject: pinctrl: zynq: fix DEFINE_ZYNQ_PINMUX_FUNCTION_MUX macro +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Masahiro Yamada + +commit 4f652cea020aac42972cb7c9788b470ed45aa228 upstream. + +The offset to the mux register is missing. + +Fixes: add958cee967 "pinctrl: Add driver for Zynq" +Signed-off-by: Masahiro Yamada +Reviewed-by: Sören Brinkmann +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/pinctrl/pinctrl-zynq.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/pinctrl/pinctrl-zynq.c ++++ b/drivers/pinctrl/pinctrl-zynq.c +@@ -714,12 +714,13 @@ static const char * const gpio0_groups[] + .mux_val = mval, \ + } + +-#define DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(fname, mval, mux, mask, shift) \ ++#define DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(fname, mval, offset, mask, shift)\ + [ZYNQ_PMUX_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + .mux_val = mval, \ ++ .mux = offset, \ + .mux_mask = mask, \ + .mux_shift = shift, \ + } diff --git a/queue-4.1/pinctrl-zynq-fix-offset-address-for-sd0-sd1-_wp_cd_sel.patch b/queue-4.1/pinctrl-zynq-fix-offset-address-for-sd0-sd1-_wp_cd_sel.patch new file mode 100644 index 00000000000..8881a692055 --- /dev/null +++ b/queue-4.1/pinctrl-zynq-fix-offset-address-for-sd0-sd1-_wp_cd_sel.patch @@ -0,0 +1,49 @@ +From 5cf021d52026c0e998756a3bdb475aae2e8a68a4 Mon Sep 17 00:00:00 2001 +From: Masahiro Yamada +Date: Wed, 20 May 2015 17:42:31 +0900 +Subject: pinctrl: zynq: fix offset address for {SD0,SD1}_WP_CD_SEL +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Masahiro Yamada + +commit 5cf021d52026c0e998756a3bdb475aae2e8a68a4 upstream. + +The address for SD0_WP_CD_SEL, SD1_WP_CD_SEL is 0xf8000830, +0xf8000834, respectively. + +Each offset address must be prefixed with 0x. + +Fixes: add958cee967 "pinctrl: Add driver for Zynq" +Signed-off-by: Masahiro Yamada +Reviewed-by: Sören Brinkmann +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/pinctrl/pinctrl-zynq.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/pinctrl/pinctrl-zynq.c ++++ b/drivers/pinctrl/pinctrl-zynq.c +@@ -745,15 +745,15 @@ static const struct zynq_pinmux_function + DEFINE_ZYNQ_PINMUX_FUNCTION(spi1, 0x50), + DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0, 0x40), + DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0_pc, 0xc), +- DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_wp, 0, 130, ZYNQ_SDIO_WP_MASK, ++ DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_wp, 0, 0x130, ZYNQ_SDIO_WP_MASK, + ZYNQ_SDIO_WP_SHIFT), +- DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_cd, 0, 130, ZYNQ_SDIO_CD_MASK, ++ DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_cd, 0, 0x130, ZYNQ_SDIO_CD_MASK, + ZYNQ_SDIO_CD_SHIFT), + DEFINE_ZYNQ_PINMUX_FUNCTION(sdio1, 0x40), + DEFINE_ZYNQ_PINMUX_FUNCTION(sdio1_pc, 0xc), +- DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_wp, 0, 134, ZYNQ_SDIO_WP_MASK, ++ DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_wp, 0, 0x134, ZYNQ_SDIO_WP_MASK, + ZYNQ_SDIO_WP_SHIFT), +- DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_cd, 0, 134, ZYNQ_SDIO_CD_MASK, ++ DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_cd, 0, 0x134, ZYNQ_SDIO_CD_MASK, + ZYNQ_SDIO_CD_SHIFT), + DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor, 4), + DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor_cs1, 8),