From: Greg Kroah-Hartman Date: Mon, 22 Apr 2013 16:40:01 +0000 (-0700) Subject: 3.4-stable patches X-Git-Tag: v3.8.9~14 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=5940d73846970513f3bf31b821ba9e5f9a62dae4;p=thirdparty%2Fkernel%2Fstable-queue.git 3.4-stable patches added patches: perf-treat-attr.config-as-u64-in-perf_swevent_init.patch perf-x86-fix-offcore_rsp-valid-mask-for-snb-ivb.patch --- diff --git a/queue-3.4/perf-treat-attr.config-as-u64-in-perf_swevent_init.patch b/queue-3.4/perf-treat-attr.config-as-u64-in-perf_swevent_init.patch new file mode 100644 index 00000000000..c02236d436c --- /dev/null +++ b/queue-3.4/perf-treat-attr.config-as-u64-in-perf_swevent_init.patch @@ -0,0 +1,41 @@ +From 8176cced706b5e5d15887584150764894e94e02f Mon Sep 17 00:00:00 2001 +From: Tommi Rantala +Date: Sat, 13 Apr 2013 22:49:14 +0300 +Subject: perf: Treat attr.config as u64 in perf_swevent_init() + +From: Tommi Rantala + +commit 8176cced706b5e5d15887584150764894e94e02f upstream. + +Trinity discovered that we fail to check all 64 bits of +attr.config passed by user space, resulting to out-of-bounds +access of the perf_swevent_enabled array in +sw_perf_event_destroy(). + +Introduced in commit b0a873ebb ("perf: Register PMU +implementations"). + +Signed-off-by: Tommi Rantala +Cc: Peter Zijlstra +Cc: davej@redhat.com +Cc: Paul Mackerras +Cc: Arnaldo Carvalho de Melo +Link: http://lkml.kernel.org/r/1365882554-30259-1-git-send-email-tt.rantala@gmail.com +Signed-off-by: Ingo Molnar +Signed-off-by: Greg Kroah-Hartman + +--- + kernel/events/core.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/kernel/events/core.c ++++ b/kernel/events/core.c +@@ -5126,7 +5126,7 @@ static void sw_perf_event_destroy(struct + + static int perf_swevent_init(struct perf_event *event) + { +- int event_id = event->attr.config; ++ u64 event_id = event->attr.config; + + if (event->attr.type != PERF_TYPE_SOFTWARE) + return -ENOENT; diff --git a/queue-3.4/perf-x86-fix-offcore_rsp-valid-mask-for-snb-ivb.patch b/queue-3.4/perf-x86-fix-offcore_rsp-valid-mask-for-snb-ivb.patch new file mode 100644 index 00000000000..523d5a3276d --- /dev/null +++ b/queue-3.4/perf-x86-fix-offcore_rsp-valid-mask-for-snb-ivb.patch @@ -0,0 +1,66 @@ +From f1923820c447e986a9da0fc6bf60c1dccdf0408e Mon Sep 17 00:00:00 2001 +From: Stephane Eranian +Date: Tue, 16 Apr 2013 13:51:43 +0200 +Subject: perf/x86: Fix offcore_rsp valid mask for SNB/IVB + +From: Stephane Eranian + +commit f1923820c447e986a9da0fc6bf60c1dccdf0408e upstream. + +The valid mask for both offcore_response_0 and +offcore_response_1 was wrong for SNB/SNB-EP, +IVB/IVB-EP. It was possible to write to +reserved bit and cause a GP fault crashing +the kernel. + +This patch fixes the problem by correctly marking the +reserved bits in the valid mask for all the processors +mentioned above. + +A distinction between desktop and server parts is introduced +because bits 24-30 are only available on the server parts. + +This version of the patch is just a rebase to perf/urgent tree +and should apply to older kernels as well. + +Signed-off-by: Stephane Eranian +Cc: peterz@infradead.org +Cc: jolsa@redhat.com +Cc: ak@linux.intel.com +Signed-off-by: Ingo Molnar +Signed-off-by: Greg Kroah-Hartman + +--- + arch/x86/kernel/cpu/perf_event_intel.c | 14 ++++++++++++-- + 1 file changed, 12 insertions(+), 2 deletions(-) + +--- a/arch/x86/kernel/cpu/perf_event_intel.c ++++ b/arch/x86/kernel/cpu/perf_event_intel.c +@@ -126,8 +126,14 @@ static struct event_constraint intel_gen + }; + + static struct extra_reg intel_snb_extra_regs[] __read_mostly = { +- INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), +- INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), ++ INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0), ++ INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1), ++ EVENT_EXTRA_END ++}; ++ ++static struct extra_reg intel_snbep_extra_regs[] __read_mostly = { ++ INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), ++ INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), + EVENT_EXTRA_END + }; + +@@ -1852,6 +1858,10 @@ __init int intel_pmu_init(void) + x86_pmu.event_constraints = intel_snb_event_constraints; + x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints; + x86_pmu.extra_regs = intel_snb_extra_regs; ++ if (boot_cpu_data.x86_model == 45) ++ x86_pmu.extra_regs = intel_snbep_extra_regs; ++ else ++ x86_pmu.extra_regs = intel_snb_extra_regs; + /* all extra regs are per-cpu when HT is on */ + x86_pmu.er_flags |= ERF_HAS_RSP_1; + x86_pmu.er_flags |= ERF_NO_HT_SHARING; diff --git a/queue-3.4/series b/queue-3.4/series index a79a0928eb2..a49ca563dd1 100644 --- a/queue-3.4/series +++ b/queue-3.4/series @@ -15,3 +15,5 @@ ath9k_htc-accept-1.x-firmware-newer-than-1.3.patch ath9k_hw-change-ar9580-initvals-to-fix-a-stability-issue.patch ssb-implement-spurious-tone-avoidance.patch crypto-algif-suppress-sending-source-address-information.patch +perf-treat-attr.config-as-u64-in-perf_swevent_init.patch +perf-x86-fix-offcore_rsp-valid-mask-for-snb-ivb.patch