From: Robert Hoo Date: Thu, 5 Jul 2018 09:09:57 +0000 (+0800) Subject: i386: Add CPUID bit for WBNOINVD X-Git-Tag: v3.1.0-rc0~135^2~3 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=59a80a19ca31a6fff9fdbb6b4cf55a5a0767c3bc;p=thirdparty%2Fqemu.git i386: Add CPUID bit for WBNOINVD WBNOINVD: Write back and do not invalidate cache, enumerated by CPUID.(EAX=80000008H, ECX=0):EBX[bit 9]. Signed-off-by: Robert Hoo Message-Id: <1530781798-183214-5-git-send-email-robert.hu@linux.intel.com> Signed-off-by: Eduardo Habkost --- diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 3e25773d26f..4f08cedfcf2 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1028,7 +1028,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { .feat_names = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, + NULL, "wbnoinvd", NULL, NULL, "ibpb", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 4a95c636403..9cad5812cd4 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -694,6 +694,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities*/ #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */ +#define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) /* Write back and + do not invalidate cache */ #define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction Barrier */ #define CPUID_XSAVE_XSAVEOPT (1U << 0)